Granted Patent B2

US 7,829,411 · App. 10/503,046 · Granted Nov 9, 2010

Abstract

Claims (19)

1. A method for forming a high quality oxide layer of different thickness over a first and a second semiconductor region in one processing step, comprising the steps of:

producing a doped gate stack that includes the first semiconductor region by growing a tunnel oxide on the semiconductor,

depositing floating gate polysilicon on the tunnel oxide,

doping the floating gate polysilicon, thus forming doped floating gate polysilicon,

depositing an interlayer dielectric on the doped floating gate polysilicon, and

depositing control gate polysilicon on the interlayer dielectric;

doping the first semiconductor region, including the control gate polysilicon, with a dopant concentration that is higher than a dopant concentration of the second semiconductor region, and

oxidising both the first and the second semiconductor regions during the same processing step at a temperature between 500° C. and 650° C. to form the oxide layer predominantly from portions of the first and second semiconductor regions that are oxidized, the oxide layer having a thickness over the first semiconductor region that is at least two times thicker than a thickness of the oxide layer over the second semiconductor region.

2. A method according to claim 1 , wherein the dopant concentration of the first semiconductor region is at least a factor 10 higher than the dopant concentration of the second semiconductor region, and wherein the thickness of the oxide layer over the first semiconductor region is at least 10 times thicker than the thickness of the oxide region over the second semiconductor region.

3. A method according to claim 2 , wherein the dopant concentration of the first semiconductor region is at least 1×10 21 cm −3 .

4. A method according to claim 1 , wherein the doping step of the first semiconductor region is carried out with n-type dopants.

5. A method according to claim 1 , wherein the doping step of the first semiconductor region is carried out with p-type dopants.

6. A method according to claim 1 , further comprising a step of patterning the doped gate stack.

7. A method according to claim 1 , wherein the oxidising step is a wet oxidation process.

8. A method according to claim 1 , wherein the oxidizing step is accomplished without depositing an oxide layer on the semiconductor regions.

9. A method according to claim 1 , wherein the second semiconductor region is a substrate and part of the oxide layer that is formed over the substrate forms a gate oxide of an access transistor.

10. The method of claim 1 , wherein the step of oxidising both the first and the second semiconductor regions includes using the dopants at their respective concentrations in the first and second semiconductor regions to control the relative thicknesses of the oxide layer over the first and second semiconductor regions to set the thickness of the oxide layer over the first semiconductor region to at least 10 times thicker than the thickness of the oxide region over the second semiconductor region.

11. The method of claim 1 , further including the step of forming a memory gate stack adjacent to the oxide layer of the second semiconductor region, wherein the oxide layer acts as an isolating spacer between the memory gate stack and the doped gate stack.

12. The method of claim 1 , wherein the step of oxidizing is implemented at a temperature less than 600° C.

Assignments (14)