Multilayer stack with compensated resonant circuit
View Patent ↗A metallization structure in a multilayer stack, which is arranged at a distance from a ground electrode, is characterized in that the metallization structure has a capacitor electrode and a line that acts as a coil, where the capacitor electrode and the line are arranged in a common plane which lies parallel with the ground electrode at a distance h 1 , and in that formula (I) where w is the width of the line.
1. A multilayer stack comprising:
a dielectric layer and one or more surrounding dielectric layers situated above or below the dielectric layer, a dielectric constant of the dielectric layer being greater than a dielectric constant of the surrounding dielectric layers, and
a metallization structure which is arranged on the dielectric layer and is arranged at a distance from a ground electrode, wherein the metallization structure has a capacitor electrode and a line that acts as a coil, where the capacitor electrode and the line are arranged in a common plane which lies parallel to the ground electrode at a distance h 1 , and wherein:
w
h
1
>
3
,
where w is the width of the line, wherein:
ɛ
medium
·
d
ɛ
ɛ
·
d
medium
>
5
wherein the dielectric constant of and a thickness of the dielectric layer are ε medium and d medium , respectively, and the dielectric constant of and a thickness of the surrounding dielectric layers are ε and d ε , respectively.
2. A metallization structure as claimed in claim 1 , further comprising:
a second ground electrode, the common plane comprising the capacitor electrode and the line being arranged parallel to said second ground electrode at a distance h 2 , and the common plane comprising the capacitor electrode and the line being between the first and second ground electrodes, where
w
h
2
>
3.
3. A multilayer stack as claimed in claim 2 , further comprising one or more additional metallization structures in the common plane, wherein
ɛ
medium
·
d
min
ɛ
·
d
medium
>
7
,
where d min is the minimum distance to a nearest metallization structure in the plane, and wherein the dielectric constant of and a thickness of the dielectric layer are ε medium and d medium , respectively, and the dielectric constant of the surrounding dielectric layers is ε.
4. A multilayer stack as claimed in claim 2 , wherein the multilayer stack further comprises magnetic layers.
5. A multilayer stack as claimed in claim 2 , produced in a multilayer laminate process.
6. A multilayer stack as claimed in claim 2 , produced in a Low Temperature Cofire Ceramic (LTCC) process.
7. A multilayer stack comprising:
a dielectric layer and one or more surrounding dielectric layers situated above or below the dielectric layer, a dielectric constant of the dielectric layer being greater than a dielectric constant of the surrounding dielectric layers, and
a metallization structure which is arranged on the dielectric layer and is arranged at a distance from a ground electrode, wherein the metallization structure has a capacitor electrode and a line that acts as a coil, where the capacitor electrode and the line are arranged in a common plane which lies parallel to the ground electrode at a distance h 1 , and wherein:
w
h
1
>
3
,
where w is the width of the line, wherein the multilayer stack is produced in a Low Temperature Cofire Ceramic (LTCC) process.
8. A metallization structure as claimed in claim 7 , further comprising:
a second ground electrode, the common plane comprising the capacitor electrode and the line being arranged parallel to said second ground electrode at a distance h 2 , and the common plane comprising the capacitor electrode and the line being between the first and second ground electrodes, where
w
h
2
>
3.
9. A multilayer stack as claimed in claim 8 , further comprising one or more additional metallization structures in the common plane, wherein
ɛ
medium
·
d
min
ɛ
·
d
medium
>
7
,
where d min is the minimum distance to a nearest metallization structure in the plane, and wherein the dielectric constant of and a thickness of the dielectric layer are ε medium and d medium , respectively, and the dielectric constant of the surrounding dielectric layers is ε.
10. A multilayer stack as claimed in claim 8 , wherein the multilayer stack further comprises magnetic layers.
11. A multilayer stack as claimed in claim 8 , produced in a multilayer laminate process.
12. A multilayer stack comprising:
a dielectric layer and one or more surrounding dielectric layers situated above or below the dielectric layer, a dielectric constant of the dielectric layer being greater than a dielectric constant of the surrounding dielectric layers;
a metallization structure which is arranged on the dielectric layer and is arranged at a distance from a ground electrode, wherein the metallization structure has a capacitor electrode and a line that acts as a coil, where the capacitor electrode and the line are arranged in a common plane which lies parallel to the ground electrode at a distance h 1 , and wherein
w
h
1
>
3
,
where w is the width of the line;
a second ground electrode, the common plane comprising the capacitor electrode and the line being arranged parallel to said second ground electrode at a distance h 2 , and the common plane comprising the capacitor electrode and the line being between the first and second ground electrodes, where
w
h
2
>
3
;
and
one or more additional metallization structures in the common plane, wherein
ɛ
medium
·
d
min
ɛ
·
d
medium
>
7
,
where d min is the minimum distance to a nearest metallization structure in the plane, and wherein the dielectric constant of and a thickness of the dielectric layer are ε medium and d medium , respectively, and the dielectric constant of the surrounding dielectric layers is ε.
13. The multilayer stack of claim 12 ,
ɛ
medium
·
d
ɛ
ɛ
·
d
medium
>
5
wherein the dielectric constant of and a thickness of the dielectric layer are ε medium and d medium , respectively, and the dielectric constant of and a thickness of the surrounding dielectric layers are ε and d ε , respectively.
14. The multilayer stack of claim 12 , wherein the multilayer stack further comprises magnetic layers.
15. The multilayer stack of claim 12 , wherein the multilayer stack is produced in a multilayer laminate process.
16. The multilayer stack of claim 12 , wherein the multilayer stack is produced in a LTCC process.
17. A multilayer stack comprising:
a dielectric layer and one or more surrounding dielectric layers situated above or below the dielectric layer, a dielectric constant of the dielectric layer being greater than a dielectric constant of the surrounding dielectric layers;
a metallization structure which is arranged on the dielectric layer and is arranged at a distance from a ground electrode, wherein the metallization structure has a capacitor electrode and a line that acts as a coil, where the capacitor electrode and the line are arranged in a common plane which lies parallel to the ground electrode at a distance h 1 , and wherein
w
h
1
>
3
,
where w is the width of the line;
a second ground electrode, the common plane comprising the capacitor electrode and the line being arranged parallel to said second ground electrode at a distance h 2 , and the common plane comprising the capacitor electrode and the line being between the first and second ground electrodes, where
w
h
2
>
3
;
and
magnetic layers.
18. The multilayer stack of claim 17 ,
ɛ
medium
·
d
ɛ
ɛ
·
d
medium
>
5
wherein the dielectric constant of and a thickness of the dielectric layer are ε medium and d medium , respectively, and the dielectric constant of and a thickness of the surrounding dielectric layers are ε and d ε , respectively.
19. The multilayer stack of claim 17 , wherein the multilayer stack is produced in a multilayer laminate process.
20. The multilayer stack of claim 17 , wherein the multilayer stack is produced in a LTCC process.