High performance CMOS device structures and method of manufacture
View Patent ↗A semiconductor device structure includes at least two field effect transistors formed on same substrate, the first field effect transistor includes a spacer having a first width, the second field effect transistor includes a compressive spacer having a second width, the first width being different than said second width. Preferably, the first width is narrower than the second width. A tensile stress dielectric film forms a barrier etch stop layer over the transistors.
1. A semiconductor device structure, comprising:
at least first and second field effect transistors disposed on a substrate;
said first field effect transistor including a first spacer having a first width;
said second field effect transistor including a second spacer having a second width;
wherein said first spacer and second spacer include a first compressive stress material, and said structure further comprises a tensile stress material disposed on said at least first and second field effect transistors.
2. The structure as claimed in claim 1 , wherein said first field effect transistor is an nFET and said second field effect transistor is a pFET.
3. The structure as claimed in claim 1 , wherein said first width is less than said second width.
4. The structure as claimed in claim 1 , wherein said structure is an inverter.
5. The structure as claimed in claim 1 , wherein said structure includes a width transition region located approximately in a middle region between said transistors.
6. The structure as claimed in claim 1 , wherein said first spacer includes an I-shaped part and said second spacer includes an L-shaped part.
7. The structure as claimed in claim 1 , wherein said second spacer includes an L-shaped part and said first compressive stress material.
8. The structure as claimed in claim 1 , wherein said first width is a substantially uniform width in a range of about 10 nm to about 30 nm, and said second width has a maximum width in a range of about 50 nm to about 120 nm.
9. The structure as claimed in claim 1 , wherein said first compressive stress material has a substantially uniform stress in a range of about −3E9 dynes/cm 2 to about −3E11 dynes/cm 2 .
10. The structure claimed in claim 1 , wherein said tensile stress material has a substantially uniform film thickness in a range of about 20 nm to about 100 nm and a substantially uniform stress in a range of approximately 4E9 dynes/cm 2 to approximately 4E11 dynes/cm 2 .
11. The structure as claimed in claim 1 , wherein said second spacer includes a second compressive stress material having a stress in a range of approximately −2E9 dynes/cm 2 to approximately 2E9 dynes/cm 2 .
12. The structure as claimed in claim 1 , wherein said first compressive stress material is a dielectric.
13. The structure as claimed in claim 1 , wherein said first compressive stress material is silicon nitride.
14. The structure as claimed in claim 1 , wherein said tensile stress material is SiN.
15. The structure as claimed in claim 1 , wherein said first width is about 50 nm, and said second width has a maximum width of about 90 nm.
16. The structure as claimed in claim 1 , wherein said tensile stress material is a layer having a substantially uniform thickness in a range of about 20 nm to about 100 nm.
17. The structure as claimed in claim 1 , wherein said substrate is a silicon substrate.
18. The structure as claimed in claim 1 , wherein said substrate comprises GaAs.