Patent Assignment
Reel/Frame 041741/0358
Assignment of Assignor's Interest
Recorded: 2017-02-17
Pages: 8
Assignor
GLOBALFOUNDRIES INC.
Executed: 2016-12-07
Assignee
AURIGA INNOVATIONS, INC.
303 TERRY FOX DRIVE, SUITE 300, OTTAWA, K2K 3J1, CANADA
Covered Properties
(84)
Plug Strap Process Utilizing Selective Nitride and Oxide Etches
Patent:
5,545,581 →
Application:
08/350,445 →
Metal-Insulator-Metal Capacitor
Patent:
5,926,359 →
Application:
08/626,310 →
Semiconductor Devices Having Backside Probing Capability
Patent:
5,990,562 →
Application:
08/806,570 →
Copper Stud Structure with Refractory Metal Liner
Patent:
6,150,723 →
Application:
08/941,857 →
Semiconductor Devices Having Backside Probing Capability
Patent:
6,078,057 →
Application:
09/010,881 →
Method and Structure for Increasing the Threshold Voltage of a Corner Device
Patent:
6,097,069 →
Application:
09/102,196 →
Self-Aligned Dynamic Threshold Cmos Device
Patent:
6,159,807 →
Application:
09/157,691 →
Method for Forming Electromigration-Resistant Structures by Doping
Patent:
6,268,291 →
Application:
09/204,185 →
Metal-Insulator-Metal Capacitor
Patent:
6,635,527 →
Application:
09/318,867 →
Method for Forming Co-W-P-Au Films
Patent:
6,323,128 →
Application:
09/320,499 →
Self-Aligned Contact Areas for Sidewall Image Transfer Formed Conductors
Patent:
6,566,759 →
Application:
09/379,453 →
Method for Making Semiconductor Devices Having Backside Probing Capability
Patent:
6,245,587 →
Application:
09/501,920 →
Semiconductor Structure and Manufacturing Method
Patent:
6,365,328 →
Application:
09/522,883 →
Self-Aligned Dynamic Threshold Cmos Device
Patent:
6,300,657 →
Application:
09/536,503 →
Copper Stud Structure with Refractory Metal Liner
Patent:
6,300,236 →
Application:
09/553,581 →
Novel CMOS device structures and method of making same
Patent:
6,303,450 →
Application:
09/717,971 →
Semiconductor Devices Having Backside Probing Capability
Semiconductor Devices Containing a Discontinuous Cap Layer and Methods for Forming Same
Method of Fabricating SIO2 Spacers and Annealing Caps
Carbon-Graded Layer for Improved Adhesion of Low-K Dielectrics to Silicon Substrates
Method for Forming Electromigration-Resistant Structures by Doping
Method for Forming Co-W-P-Au Films
Stacked Fill Structures for Support of Dielectric Layers
Integration of Dual Workfunction Metal Gate Cmos Devices
Electrically Porous on-Chip Decoupling/Shielding Layer
Patent:
6,518,670 →
Application:
10/091,643 →
Method and Structure for Ultra-Low Contact Resistance Cmos Formed by Vertically Self-Aligned COSI2 on Raised Source Drain Si/Sige Device
Multi-Height Finfets
Semiconductor Device Structure Including Multiple Fets Having Different Spacer Widths
Methods for Fabricating Electrical Connections to Semiconductor Structures Incorporating Low-K Dielectric Materials
Patent:
6,630,395 →
Application:
10/280,266 →
Method of Manufacture of Mosfet Device with in-Situ Doped, Raised Source and Drain Structures
Stress Inducing Spacers
Patternable Low Dielectric Constsnt Materials and Their Use in Ulsi Interconnection
Stacked Fill Structures for Support of Dielectric Layers
Self-Aligned Contact Areas for Sidewall Image Transfer Formed Conductors
Carbon-Graded Layer for Improved Adhesion of Low-K Dielectrics to Silicon Substrates
Method and structure for ultra-low contact resistance CMOS formed by vertically self-aligned CoSi2 on raised source drain Si/SiGe device
Semiconductor Memory Device with Increased Node Capacitance
Dual Damascene Interconnect Structures Having Different Materials for Line and via Conductors
Hybrid Planar and Finfet Cmos Devices
High Performance Cmos Device Structures and Method of Manufacture
Method for Avoiding Oxide Undercut During Pre-Silicide Clean for Thin Spacer Fets
Methods and Systems for Fabricating Electrical Connections to Semiconductor Structures Incorporating Low-K Dielectric Materials
Patent:
6,888,224 →
Application:
10/609,784 →
Metal-Insulator-Metal Capacitor
High Performance Stress-Enhanced Mosfets Using Si:C and Sige Epitaxial Source/Drain and Method of Manufacture
Structure and Method for Forming a Dielectric Chamber and Electronic Device Including the Dielectric Chamber
Sacrificial Inorganic Polymer Intermetal Dielectric Damascene Wire and via Liner
Method and Structure for Controlling Stress in a Transistor Channel
Patterned Strained Semiconductor Substrate and Device
Three-Mask Method of Constructing the Final Hard Mask Used for Etching the Silicon Fins for Finfets
Patent:
6,951,784 →
Application:
10/710,822 →
Method of Fabricating Copper Damascene and Dual Damascene Interconnect Wiring
Complementary Transistors Having Different Source and Drain Extension Spacing Controlled by Different Spacer Sizes
Cmos Silicide Metal Gate Integration
Mosfet Structure with High Mechanical Stress in the Channel
Selective Implementation of Barrier Layers to Achieve Threshold Voltage Control in Cmos Device Fabrication with High K Dielectrics
Mosfet Device with in-Situ Doped, Raised Source and Drain Structures
Stress Inducing Spacers
Selective Implementation of Barrier Layers to Achieve Threshold Voltage Control in Cmos Device Fabrication with High-K Dielectrics
Hybrid Planar and Finfet Cmos Devices
Structure and Method for Forming a Dielectric Chamber and Electronic Device Including the Dielectric Chamber
Ic Tiling Pattern Method, Ic So Formed and Analysis Method
Dual Damascene Interconnect Structures Having Different Materials for Line and via Conductors
Complementary Transistors Having Different Source and Drain Extension Spacing Controlled by Different Spacer Sizes
Method for Avoiding Oxide Undercut During Pre-Silicide Clean for Thin Spacer Fets
Patternable Low Dielectric Constant Materials and Their Use in Ulsi Interconnection
Cmos Silicide Metal Gate Integration
Selective Implementation of Barrier Layers to Achieve Threshold Voltage Control in Cmos Device Fabrication with High K Dielectrics
Method of Fabricating Copper Damascene and Dual Damascene Interconnect Wiring
Sacrificial Inorganic Polymer Intermetal Dielectric Damascene Wire and via Liner
Dual Damascene Interconnect Structures Having Different Materials for Line and via Conductors
High Performance Stress-Enhanced Mosfets Using Si:C and Sige Epitaxial Source/Drain and Method of Manufacture
High Performance Cmos Device Structures and Method of Manufacture
Sacrificial Inorganic Polymer Intermetal Dielectric Damascene Wire and via Liner
Patterned Strained Semiconductor Substrate and Device
Patternable Low Dielectric Constant Materials and Their Use in Ulsi Interconnection
Patterned Strained Semiconductor Substrate and Device
Method and Structure for Controlling Stress in a Transistor Channel
Cmos Silicide Metal Gate Integration
Selective Implementation of Barrier Layers to Achieve Treshold Voltage Control in Cmos Device Fabrication with High K Dielectrics
Selective Implementation of Barrier Layers to Achieve Threshold Voltage Control in Cmos Device Fabrication with High-K Dielectrics
Copper Damascene and Dual Damascene Interconnect Wiring
Patterned Strained Semiconductor Substrate and Device
Sacrificial Inorganic Polymer Intermetal Dielectric Damascene Wire and via Liner
Selective Implementation of Barrier Layers to Achieve Threshold Voltage Control in Cmos Device Fabrication with High-K Dielectrics
Method of Fabricating Copper Damascene and Dual Damascene Interconnect Wiring
Related Assignments
(6)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
May 8, 2015
From: QIMONDA AG
To: INFINEON TECHNOLOGIES AG
Reel/Frame 035623/0001 →
Assignment of Assignor's Interest
Sep 3, 2015
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: GLOBALFOUNDRIES U.S. 2 LLC
Reel/Frame 036550/0001 →
Assignment of Assignor's Interest
Oct 5, 2015
From: GLOBALFOUNDRIES U.S. 2 LLC; GLOBALFOUNDRIES U.S. INC.
To: GLOBALFOUNDRIES INC.
Reel/Frame 036779/0001 →
Security Agreement
Nov 29, 2018
From: GLOBALFOUNDRIES INC.
To: WILMINGTON TRUST, NATIONAL ASSOCIATION
Reel/Frame 049490/0001 →
Release of Security Interest
Nov 20, 2020
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES INC.
Reel/Frame 054636/0001 →
Release of Security Interest
May 12, 2021
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES U.S. INC.
Reel/Frame 056987/0001 →