Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high-k dielectrics
View Patent ↗The present invention provides a semiconductor structure including a semiconductor substrate having a plurality of source and drain diffusion regions located therein, each pair of source and drain diffusion regions are separated by a device channel. The structure further includes a first gate stack of pFET device located on top of some of the device channels, the first gate stack including a high-k gate dielectric, an insulating interlayer abutting the gate dielectric and a fully silicided metal gate electrode abutting the insulating interlayer, the insulating interlayer includes an insulating metal nitride that stabilizes threshold voltage and flatband voltage of the p-FET device to a targeted value and is one of aluminum oxynitride, boron nitride, boron oxynitride, gallium nitride, gallium oxynitride, indium nitride and indium oxynitride. A second gate stack of an nFET devices is located on top remaining device channels, the second gate stack including a high-k gate dielectric and a fully silicided gate electrode located directly atop the high-k gate dielectric.
1. A complementary metal oxide semiconductor (CMOS) structure comprising:
a semiconductor substrate having a first device region comprising n-type semiconductor devices and a second device region comprising p-type semiconductor device, wherein said first device region comprises at least one first gate stack comprising a first high-k gate dielectric and a first fully silicided gate electrode that are in direct contact, and wherein said second device region comprises at least one second gate stack comprising a second high-k gate dielectric, an insulating interlayer atop said high-k gate dielectric, and a second fully silicided gate electrode atop said insulating interlayer, wherein said insulating interlayer is selected from the group consisting of aluminum nitride (AlN), aluminum oxynitride (AlO x N y ), boron nitride (BN), boron oxynitride (BO x N y ), gallium nitride (GaN), gallium oxynitride (GaON), indium nitride (InN), indium oxynitride (InON) and combinations thereof, wherein said insulating interlayer stabilizes said p-type semiconductor devices threshold voltage and flatband voltage without shifting said n-type semiconductor devices threshold voltage and flatband voltage.
2. The CMOS structure of claim 1 wherein said first device region comprises nFET devices and said second device region comprises pFET devices.
3. The CMOS structure of claim 1 wherein said semiconductor substrate comprises Si, SiGe, silicon-on-insulators or silicon germanium-on-insulators.
4. The CMOS structure of claim 2 wherein said first device region further comprises n-type doped source/drain portions of said substrate adjacent to said at least one first gate stack and said second device region further comprises p-type doped source/drain portions of said substrate adjacent to said at least one second gate stack.
5. The CMOS structure of claim 2 wherein said first high-k gate dielectric and said second high-k gate dielectric comprise the same material or comprise a different material.
6. The CMOS structure of claim 5 wherein said first high-k gate dielectric and said second high-k gate dielectric comprises HfO 2 , ZrO 2 , Al 2 O 3 , TiO 2 , La 2 O 3 , SrTiO 3 , LaAlO 3 , Y 2 O 3 , SiO 2 , nitrided SiO 2 or silicates, nitrides or nitrided silicates thereof.
7. The CMOS structure of claim 2 wherein said insulating interlayer comprises an insulating metal nitride having a thickness ranging from about 1 Å to about 25 Å.
8. The CMOS structure of claim 2 wherein said insulating interlayer comprises AlN or AlO x N y .
9. The semiconductor structure of claim 2 wherein said first fully silicided metal gate and said second fully silicided metal gate electrode comprises a silicide of at least one of Ti, Ta, W, Co, Ni, Pt, Pd, or alloys thereof.
10. The semiconductor structure of claim 2 wherein said first fully silicided metal gate electrode and said second fully silicided metal gate electrode comprise NiSi or NiPtSi.
11. The semiconductor structure of claim 2 wherein said first fully silicided metal gate electrode and said second fully silicided metal gate electrode comprise a germinide of at least one of Ti, Ta, W, Ni, Pt, Pd, or alloys thereof.
12. The semiconductor structure of claim 2 wherein said first fully silicided metal gate electrode and said second fully silicided metal gate electrode comprise NiGe or NiPtGe.
13. The semiconductor structure of claim 2 wherein said first fully silicided metal gate electrode and said second fully silicided metal gate electrode contain B, Al, Ga, In, N, P, As, Sb, Bi or mixtures thereof.
14. The semiconductor structure of claim 4 wherein said first fully silicided metal gate electrode and said second fully silicided metal gate electrode have a first thickness greater than 500 Å.
15. The semiconductor structure of claim 14 wherein said n-type doped source/drain portions and said p-type doped source/drain portions have a silicided surface of a second thickness, wherein said first thickness of said first fully silicided metal gate electrode and said second fully silicided metal gate electrode is greater than said second thickness of said n-type doped source/drain portions and said p-type doped source/drain portions.
16. The semiconductor structure of claim 15 wherein said second thickness is less than 200 Å.