Patterned strained semiconductor substrate and device

1. An electrical device, comprising:

a pattern of strained material and relaxed material formed on a substrate;

a vertical insulating layer formed on sidewalls of a recess in the substrate;

a buffer layer formed within the sidewalls of a recess and directly on an interior portion of the substrate exposed by the recess, the buffer layer having a lattice constant/structure mismatch with the substrate; and

a relaxed layer formed within the sidewalls of the recess and directly on the buffer layer, a top surface of the relaxed layer placing the strained material in one of a tensile or a compressive state,

wherein:

the strained material is formed within the sidewalls of the recess and directly on the relaxed layer;

the relaxed layer comprises a material which has a lattice constant/structure mismatch with the strained material;

the relaxed material is different than the relaxed layer; and

a material forming the buffer layer increases in concentration from a base concentration proximate the substrate to a benchmark concentration proximate the relaxed layer.

2. The electrical device of claim 1 , wherein a material that forms the insulating layer is one of an oxide and a nitride.

3. The electrical device of claim 1 , wherein:

a portion of the substrate forms the relaxed material; and

the relaxed material is located outside a confine of the sidewalls of a recess and the vertical the insulating layer.

4. An electrical device, comprising:

a pattern of strained material and relaxed material formed on a substrate;

a buffer layer formed on the substrate and having a lattice constant/structure mismatch with the substrate;

a relaxed layer formed on the buffer layer, a top surface of the relaxed layer placing the strained material in one of a tensile or a compressive state;

a recess formed in the substrate and enclosing the buffer layer, the recess having sidewalls; and

an insulating layer formed on the sidewalls,

wherein:

the relaxed layer comprises a material having a lattice constant/structure mismatch with the strained material;

the relaxed material is different than the relaxed layer;

a material forming the buffer layer increases in concentration from a base concentration proximate the substrate to a benchmark concentration proximate the relaxed layer; and

the buffer layer, the relaxed layer, and the strained material are formed in the recess within a confine of the insulating layer, and the relaxed material is formed outside the confine of the insulating layer.

5. The electrical device of claim 4 , wherein the relaxed layer and the buffer layer are selected from the group consisting of silicon carbon (SiC), silicon germanium (SiGe), Al X1 Ga X2 In X3 As Y1 P Y2 N Y3 Sb 4 , where X1, X2, X3, Y1, Y2, Y3, and Y4 represent relative proportions, each greater than or equal to zero and X1+X2+X3+Y1+Y2+Y3+Y4=1, and Zn A1 Cd A2 Se B1 Te B2 , where A1, A2, B1, and B2 are relative proportions each greater than or equal to zero and A1+A2+B1+B2=1.

6. The electrical device of claim 1 , wherein the relaxed layer and the buffer layer are selected from the group consisting of silicon carbon (SiC), silicon germanium (SiGe), Al X1 Ga X2 In X3 As Y1 P Y2 N Y3 Sb Y4 , where X1, X2, X3, Y1, Y2, Y3, and Y4 represent relative proportions, each greater than or equal to zero and X1+X2+X3+Y1+Y2+Y3+Y4=1, and Zn A1 Cd A2 Se B1 Te B2 , where A1, A2, B1, and B2 are relative proportions each greater than or equal to zero and A1+A2+B1+B2=1.

7. The electrical device of claim 1 , wherein a material forming the relaxed layer has a second base concentration proximate the buffer layer that approximately equals the benchmark concentration.

8. The electrical device of claim 1 , further comprising:

a strained device formed in the strained material; and

a non-strained device formed in the relaxed material.

9. The electrical device of claim 8 , wherein the non-strained device is formed directly on the substrate.

10. The electrical device of claim 1 , wherein:

the base concentration is at a bottom of the buffer layer; and

the benchmark concentration is at a top of the buffer layer.

11. The electrical device of claim 10 , wherein the relaxed layer has a second base concentration at a bottom of the relaxed layer that approximately equals the benchmark concentration at the top of the buffer layer.

12. The electrical device of claim 11 , wherein the relaxed layer comprises a material which has a lattice constant/structure mismatch with the strained material.

13. The electrical device of claim 12 , wherein:

the buffer layer comprises multiple layers;

each of the multiple layers has a different concentration of a material such that the concentration of the material in the buffer layer incrementally increases in equal steps from a bottommost layer to a topmost layer of the multiple layers;

the bottommost layer of the multiple layers is at the bottom of the recess and has a base concentration;

the topmost layer of the multiple layers has the benchmark concentration.

14. The electrical device of claim 1 , wherein:

the relaxed material is directly on the substrate; and

the relaxed material avoids contact with the buffer layer.

15. The electrical device of claim 1 , wherein the pattern of strained material and relaxed material comprises a single epitaxially-grown layer formed within and without the insulating layer on the sidewalls of the recess.

16. The electrical device of claim 1 , wherein a topmost surface of the strained material is coplanar with a topmost surface of the insulating layer and a topmost surface of the relaxed material.

17. The electrical device of claim 16 , wherein a bottommost surface of the insulating layer is coplanar with a bottommost surface of the buffer layer.