Sacrificial inorganic polymer intermetal dielectric damascene wire and via liner
View Patent ↗The present invention provides a method of forming a rigid interconnect structure, and the device therefrom, including the steps of providing a lower metal wiring layer having first metal lines positioned within a lower low-k dielectric; depositing an upper low-k dielectric atop the lower metal wiring layer; etching at least one portion of the upper low-k dielectric to provide at least one via to the first metal lines; forming rigid dielectric sidewall spacers in at least one via of the upper low-k dielectric; and forming second metal lines in at least one portion of the upper low-k dielectric. The rigid dielectric sidewall spacers may comprise of SiCH, SiC, SiNH, SiN, or SiO 2 . Alternatively, the via region of the interconnect structure may be strengthened with a mechanically rigid dielectric comprising SiO 2 , SiCOH, or doped silicate glass.
1. A method of forming an interconnect structure comprising the steps of:
providing a lower metal wiring layer having first metal lines located within a lower low-k dielectric;
depositing an upper low-k dielectric atop said lower metal wiring layer;
etching at least one portion of said upper low-k dielectric to provide at least one via to said first metal lines;
forming rigid dielectric sidewall spacers in said at least one via of said upper low-k dielectric, said dielectric sidewall spacers are of a material selected from the group consisting of SiCH, SiCOH, and SiO 2 ; and
forming second metal lines in said at least one portion of said upper low-k dielectric.
2. The method of claim 1 wherein said upper low-k dielectric and said lower low-k dielectric comprise materials having a dielectric constant ranging from about 1.0 to about 3.5.
3. The method of claim 1 wherein said upper low-k dielectric and said lower low-k dielectric comprise low-k polymers or low-k carbon doped oxides.
4. The method of claim 1 wherein said forming rigid dielectric sidewall spacers further comprises:
depositing a conformal rigid dielectric liner atop said upper low-k dielectric and within said at least one via; and
etching horizontal surfaces of said conformal rigid dielectric liner to form said rigid dielectric spacers positioned on vertical sidewalls of said at least one via.
5. The method of claim 4 wherein depositing a conformal rigid dielectric liner further comprises physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), high density plasma chemical vapor deposition (HDPCVD), or low pressure chemical vapor deposition (LPCVD).
6. The method of claim 5 wherein said conformal rigid dielectric liner has a thickness ranging from about 10 nm to about 100 nm.
7. The method of claim 6 wherein said etching horizontal surfaces of said conformal rigid dielectric liner further comprises an anisotropic etch process.
8. The method of claim 7 wherein said lower metal wiring layer further comprises a rigid insulating layer deposited atop said lower low-k dielectric, said rigid insulating layer material selected from the group consisting of SiC, SiO 2 , and Si 3 N 4 .