Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high k dielectrics
View Patent ↗A method of forming a CMOS structure, and the device produced therefrom, having improved threshold voltage and flatband voltage stability. The inventive method includes the steps of providing a semiconductor substrate having an nFET region and a pFET region; forming a dielectric stack atop the semiconductor substrate comprising an insulating interlayer atop a high k dielectric; removing the insulating interlayer from the nFET region without removing the insulating interlayer from the pFET region; and providing at least one gate stack in the pFET region and at least one gate stack in the nFET region. The insulating interlayer can be AlN or AlO x N y . The high k dielectric can be HfO 2 , hafnium silicate or hafnium silicon oxynitride. The insulating interlayer can be removed from the nFET region by a wet etch including a HCl/H 2 O 2 peroxide solution.
1. A method of forming a semiconductor structure comprising:
providing a semiconductor substrate;
forming a dielectric stack atop said semiconductor substrate comprising an aluminum nitride-containing insulating layer atop a hafnium silicate layer; and
selectively etching said aluminum nitride-containing insulating layer without substantially etching said hafnium silicate layer, wherein the etching comprises a wet etch comprising an etch chemistry comprising a 3:1 HCl/H 2 O 2 peroxide solution, and the etch chemistry has a pH ranging from about 1 to about 7.
2. The method of claim 1 wherein said etch chemistry has a pH ranging from about 2 to about 6.
3. The method of claim 1 further comprising forming a block mask atop a portion of said dielectric stack leaving a remaining portion of said dielectric stack exposed prior to said etching, wherein said wet etch removes said aluminum nitride-containing insulating layer from said remaining portion of said dielectric stack without substantially etching said block mask or said hafnium silicate layer.
4. The method of claim 3 wherein said block mask comprises photoresist, silicon oxides, silicon carbides, silicon nitrides, silicon carbonitrides, silsequioxanes, siloxanes, or boron phosphate silicate glass (BPSG).