Dual damascene interconnect structures having different materials for line and via conductors
View Patent ↗Methods are disclosed for forming dual damascene back-end-of-line (BEOL) interconnect structures using materials for the vias or studs which are different from those used for the line conductors, or using materials for the via liner which are different from those used for the trench liner, or having a via liner thickness different from that of the trench liner. Preferably, a thick refractory metal is used in the vias for improved mechanical strength while using only a thin refractory metal in the trenches to provide low resistance.
1. A method for forming an interconnect structure on a substrate, the substrate comprising a first layer of a first dielectric material having at least one first conductor embedded therein, the first conductor having a top surface coplanar with a top surface of the first layer of the first dielectric material, the method comprising steps of:
depositing a second layer of a second dielectric material on the first layer of first dielectric material;
forming at least one first opening in the second layer of the second dielectric material, the first opening partially exposing the first conductor;
depositing a first conductive liner on a bottom and sidewalls of the first opening
after depositing the first conductive liner, filling the first opening with a first conductive material;
removing a top portion of the first conductive material;
forming at least one second opening in the second layer of the second dielectric material, the second opening overlying the first conductive material, and the second opening having a lateral extent greater than that of the first opening; and
depositing a second conductive liner on a bottom and sidewalls of the second opening
after depositing the second conductive liner, filling the second opening with a second conductive material, wherein the second conductive material is different from the first conductive material, and the second conductive material has a top surface which is made coplanar with a top surface of the second layer of the second dielectric material.
2. The method of claim 1 , further comprising a step of depositing at least one hardmask layer on the second layer of the second dielectric material.
3. A method of claim 1 , wherein the second dielectric material is the same as the first dielectric material.
4. A method of claim 1 , wherein the second dielectric material is different from the first dielectric material.
5. A method of claim 1 , wherein the second conductive material is copper and the first conductive material is tungsten.
6. The method of claim 1 , wherein the first conductive liner is formed of material selected from the group consisting of: titanium nitride, tantalum, tantalum nitride and tungsten, and the second conductive liner is formed of a material selected from the group consisting of tantalum nitride and tantalum.
7. The method of claim 1 , wherein the second conductive liner has a thickness less than a thickness of the first conductive liner.
8. The method of claim 1 , wherein the first and second openings are formed using lithography and reactive ion etching.
9. The method of claim 1 , wherein the first opening is filled with the first conductive material by chemical vapor deposition.
10. The method of claim 1 , wherein the first conductive liner and the second conductive liner are deposited by physical vapor deposition or chemical vapor deposition.
11. The method of claim 1 , wherein the top surface of the second conductive material is made coplanar by chemical mechanical polishing.
12. The method of claim 2 , wherein the top portion of first conductive material is removed by dry etching using fluorine-based chemistry, wet etching using hydrogen peroxide, or electroetching.