Complementary transistors having different source and drain extension spacing controlled by different spacer sizes
View Patent ↗Disclosed is a method of forming an integrated circuit structure having first-type transistors, such as P-type field effect transistors (PFETs) and complementary second-type transistors, such as N-type field effect transistors (NFETs) on the same substrate. More specifically, the invention forms gate conductors above channel regions in the substrate, sidewall spacers adjacent the gate conductors, and source and drain extensions in the substrate. The sidewall spacers are larger (extend further from the gate conductor) in the PFETs than in the NFETs. The sidewall spacers align the source and drain extensions during the implanting process. Therefore, the larger sidewall spacers position (align) the source and drain implants further from the channel region for the PFETs when compared to the NFETs. Then, during the subsequent annealing processes, the faster moving PFET impurities will be restrained from diffusing too far into the channel region under the gate conductor. This prevents the short channel effect that occurs when the source and drain impurities extend too far beneath the gate conductor and short out the channel region.
1. A method of forming an integrated circuit structure having first-type transistors and second-type transistors on a same substrate, said method comprising:
forming gate conductors above channel regions in said substrate;
forming sidewall spacers adjacent said gate conductors, wherein said sidewall spacers are larger in said first-type transistors than in said second-type transistors;
forming source and drain extensions in said substrate; and
forming silicide regions between portions of said sidewall spacers and said substrate, wherein said silicide regions are larger in said first-type transistors than in said second-type transistors.
2. The method in claim 1 , wherein said process of forming said source and drain extensions forms said source and drain extensions further from said channel regions in said first-type transistors than in said second-type transistors.
3. The method in claim 1 , wherein said process of forming said source and drain extensions comprises implanting said source and drain extensions, wherein said sidewall spacers align said source and drain extensions during said implanting process.
4. The method in claim 3 , wherein said process of forming said sidewall spacers includes forming a multiple-layer sidewall spacers, wherein said sidewall spacers in said first-type transistors have more sidewall spacer layers than in said second-type transistors.
5. The method in claim 1 , wherein said process of forming said sidewall spacers includes forming an oxide liner, wherein said oxide liner is thicker in said first-type transistors than in said second-type transistors.
6. The method in claim 5 , wherein oxide liners for said first-type transistors are formed in a different processing step than oxide liners for said second-type transistors.
7. A method of forming an integrated circuit structure having P-type field effect transistors (PFETs) and N-type field effect transistors (NFETs) transistors on a same substrate, said method comprising:
forming gate conductors above channel regions in said substrate;
forming sidewall spacers adjacent said gate conductors, wherein said sidewall spacers are larger in said PFETs than in said NFETs;
forming source and drain extensions in said substrate; and
forming silicide regions between portions of said sidewall spacers and said substrate, wherein said silicide regions are larger in said PFETs than in said NFETs.
8. The method in claim 7 , wherein said process of forming said source and drain extensions forms said source and drain extensions further from said channel regions in said PFETs than in said NFETs.
9. The method in claim 7 , wherein said process of forming said source and drain extensions comprises implanting said source and drain extensions, wherein said sidewall spacers align said source and drain extensions during said implanting process.
10. The method in claim 9 , wherein said process of forming said sidewall spacers includes forming a multiple-layer sidewall spacers, wherein said sidewall spacers in said PFETs have more sidewall spacer layers than in said NFETs.
11. The method in claim 7 , wherein said process of forming said sidewall spacers includes forming an oxide liner, wherein said oxide liner is thicker in said PFETs than in said NFETs.
12. The method in claim 11 , wherein oxide liners for said PFETs are formed in a different processing step than oxide liners for said NFETs.