High performance CMOS device structures and method of manufacture
View Patent ↗A semiconductor device structure includes at least two field effect transistors formed on same substrate, the first field effect transistor includes a spacer having a first width, the second field effect transistor includes a compressive spacer having a second width, the first width being different than said second width. Preferably, the first width is narrower than the second width. A tensile stress dielectric film forms a barrier etch stop layer over the transistors.
1. A method for fabricating a semiconductor device structure, comprising:
providing a semiconductor substrate;
forming gate stacks on the substrate, extension spacers on the gate stacks, extension implants adjacent to the extension spacers, and an isolation region between at least two extension implants;
disposing a first compressive stress dielectric material onto the gate stacks, extension spacers, and extension implants;
disposing a second dielectric material with a low stress onto the first compressive stress dielectric material;
masking a first portion of the second dielectric material over one gate stack;
removing a second portion of the second dielectric material over another gate stack;
etching the first portion to form intermediate low stress spacers proximate to the one gate stack;
etching the first dielectric material to form narrow compressive spacers proximate to the another gate stack and wide compressive spacers proximate to the one gate stack;
forming source and drain implants and silicides thereon;
disposing a tensile stress dielectric material over all the spacers.
2. The method as claimed in claim 1 , wherein said step of disposing a first compressive stress dielectric material includes PECVD depositing silicon nitride.
3. The method as claimed in claim 1 , wherein said step of disposing a tensile stress dielectric material includes CVD depositing a SiN layer.