IP Library › Granted Patent US 6,949,826
Granted Patent B2
US 6,949,826 · App. 10/605,660 · Granted Sep 27, 2005

High density semiconductor package

Assignee: Advanced Semiconductor Engineering, Inc.
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Quick Facts
Patent No.
US 6,949,826
App. No.
10/605,660
Granted
Sep 27, 2005
Kind
B2
Abstract

A high density semiconductor package comprises a substrate, a first package module and a plurality of second package modules. The substrate has a surface on which the first package module and the second package modules are disposed, wherein the second package modules surround the first package module.

Claims (16)

1. A high density semiconductor package, comprising:

a substrate, having a surface;

a first package module, being disposed on the surface of the substrate; and

a plurality of second package modules, being disposed on the surface of the substrate surrounding the first package module, wherein each of the second package modules has a corner near a corresponding one side of the first package module, wherein the corner is included from two sides of a corresponding one of the second package modules and the two sides are not parallel to the corresponding one side of the first package module.

2. The high density semiconductor package as claimed in claim 1 , wherein a gap between the corner of the corresponding one of the second package modules and the corresponding one side of the first package module is larger than 2 mm.

3. The high density semiconductor package structure as claimed in claim 1 , wherein the first package module is arranged coplanar with the second package modules.

4. The high density semiconductor package as claimed in claim 1 , wherein the first package module comprises:

a chip;

a plurality of bumps located between the chip and the substrate; and

an underfill located between the chip and the substrate and enveloping the bumps.

5. The high density semiconductor package as claimed in claim 1 , wherein each of the second package modules comprises:

a chip;

a plurality of bumps located between the chip and the substrate; and

an underfill located between the chip and the substrate and enveloping the bumps.

6. The high density semiconductor package as claimed in claim 1 , wherein the first package module has four sides, and the number of the second package modules is four, respectively facing to the four sides.

7. The high density semiconductor package as claimed in claim 1 , wherein the corner of each of the second package modules face the side of the first package module by a direction substantially perpendicular to one of the sides of the first package module.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 16, 2003
From: WANG, SUNG-FEI
To: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
Reel/Frame 014047/0919 →
Priority Claims (1)
TW 91125100 A · Oct 25, 2002 · national
Continuity (1)
Related Publication 20040104475A1 · Jun 3, 2004