Granted Patent B1

US 7,257,084 · App. 10/613,776 · Granted Aug 14, 2007

Abstract

Claims (36)

1. A traffic management processor for scheduling packets for transmission across a network, comprising:

a departure time calculator for generating a departure time for each packet;

a departure time table having a plurality of rows, each having a first portion for storing the departure time for a corresponding packet and having a second portion for storing a rollover bit; and

a reset circuit coupled to the departure time calculator and to the departure time table, the reset circuit configured to reset the rollover bits from a first logic state to a second logic state at a predetermined time.

2. The traffic management processor of claim 1 , wherein the departure time calculator comprises:

a counter for generating an arrival time; and

an arithmetic logic unit coupled to the counter and configured to generate the departure in response to the arrival time.

3. The traffic management processor of claim 2 , wherein the reset circuit has an output to provide a reset signal to the departure time table, wherein the reset signal is asserted to reset the rollover bits when the counter reaches a value indicative of the predetermined time.

4. The traffic management processor of claim 1 , further comprising:

compare logic coupled to the departure time table and configured to compare the departure times with each other to determine which departure time is the earliest.

5. The traffic management processor of claim 1 , wherein each rollover bit comprises a most significant bit of the corresponding departure time.

6. A traffic management processor for scheduling packets for transmission across a network, comprising:

a counter for generating an arrival time for each packet;

an arithmetic logic unit having an input to receive the arrival time and configured to generate a departure time in response to the arrival time;

a reset circuit having an input to receive the arrival time and having an output for generating a reset signal; and

a table having a plurality of rows, each having a first portion for storing the departure time for a corresponding packet and having a second portion for storing a rollover bit, wherein the reset signal selectively resets the rollover bit from a first logic state to a second logic state.

7. The traffic management processor of claim 6 , wherein the reset circuit asserts the reset signal to reset the rollover bits when the counter generates a maximum arrival time.

8. The traffic management processor of claim 6 , wherein each rollover bit comprises a most significant bit of the corresponding departure time.

9. The traffic management processor of claim 6 , further comprising:

compare logic coupled to the table and configured to compare the departure times with each other to determine which departure time is the earliest.

10. A method for operating a packet scheduler, comprising:

determining an arrival time for each of a plurality of packets received;

calculating a departure time for each packet in response to the packet's arrival time;

storing the departure times for the plurality of packets in a departure time table;

asserting a rollover bit corresponding to each departure time; and

de-asserting the rollover bits when the arrival time reaches a maximum value.

11. The method of claim 10 , wherein the de-asserting comprises:

comparing the arrival time with the maximum value; and

selectively asserting a reset signal in response to the comparing.

12. The method of claim 11 , further comprising:

resetting the rollover bits to a logic low value in response to the reset signal.

13. The method of claim 10 , further comprising:

storing the rollover bits in the departure time table.

14. The method of claim 13 , wherein each of a plurality of rows of the departure time table stores the departure time and the rollover bit for a corresponding packet.

15. The method of claim 11 , wherein the reset signal is asserted by a reset circuit that is coupled to the departure time table.

16. The method of claim 15 , wherein the departure time is calculated by a departure time calculator that is coupled to the departure time table and to the reset circuit.

Assignments (12)