Granted Patent B1

US 6,939,766 · App. 10/616,804 · Granted Sep 6, 2005

Abstract

Claims (27)

1. A method for fabricating a flash memory device comprising:

fabricating a gate structure comprising a tunnel oxide layer, a floating gate layer, an oxide layer, and a control gate layer on a semiconductor substrate, wherein said fabricating comprises an etch process, and wherein said etch process results damage to said tunnel oxide layer;

creating a first impurity concentration in said semiconductor substrate prior to said repairing;

creating a second impurity concentration in said semiconductor substrate prior to said repairing; and

repairing damage resulting from said etch process to said tunnel oxide layer prior to creating said first impurity concentration and creating said second impurity concentration wherein said repairing said tunnel oxide layer is accomplished using a rapid thermal oxidation (RTO) process, and wherein repairing said tunnel oxide layer prior to creating said first and second impurity concentrations prevents a dopant diffusion from said first and second concentration into a channel region due to said repairing.

2. The method as recited in claim 1 , wherein said fabricating comprises fabricating a gate structure that is less than 0.21 microns (0.21μ) in length.

3. The method as recited in claim 1 , wherein said repairing comprises:

creating additional oxide material in a damaged region of said oxide layer.

4. The method as recited in claim 1 , wherein said rapid thermal oxidation process comprises exposing said semiconductor structure to a temperature of 1000° C. for a period of time not longer than 20 seconds.

5. The method as recited in claim 1 , wherein said rapid thermal oxidation process comprises selecting a plurality of process parameters wherein a portion of said tunnel oxide layer retains a uniform profile after said rapid thermal process is performed.

6. A method for fabricating a memory device comprising:

fabricating a gate structure upon a semiconductor substrate, wherein said fabricating comprises an etch process wherein said gate structure comprises an tunnel oxide layer, and wherein said etch process results in damage to said oxide layer;

depositing a dopant in a first region of said semiconductor substrate and in a second region of said semiconductor substrate; and

performing a rapid thermal oxidation (RTO) process upon said semiconductor substrate prior to said depositing said dopant in said first region and said second region of said semiconductor substrate, wherein additional oxide material is created in a damaged region of said tunnel oxide layer of said gate structure, and wherein said performing said RTO process prior to said depositing said dopant into said first and second regions prevents diffusion of said dopant into a channel region.

7. The method as recited in claim 6 , wherein said memory device comprises a flash memory device and comprising fabricating a floating gate memory structure upon said semiconductor substrate.

8. The method as recited in claim 7 , wherein said fabricating comprises fabricating a floating gate structure that is less than 0.21 microns (0.21μ) in length.

9. The method as recited in claim 6 , wherein said rapid thermal oxidation process comprises selecting a plurality of process parameters wherein a portion of said tunnel oxide layer retains a uniform profile after said rapid thermal process is performed.

10. The method as recited in claim 9 , wherein said rapid thermal oxidation process comprises exposing said semiconductor structure to a temperature of 1000° C. for a period of time not longer than 20 seconds.

11. A method for fabricating a memory device comprising:

depositing a plurality of layers upon a semiconductor substrate, wherein said plurality of layers comprises a tunnel oxide layer;

patterning said plurality of layers to create a stack gate, wherein said patterning comprises an etch process, and wherein said etch process produces a damaged region of said tunnel oxide layer;

creating a source region wherein a first impurity concentration is deposited in said semiconductor substrate;

creating a drain region wherein a second impurity concentration is deposited in said semiconductor substrate; and

performing a rapid thermal oxidation (RTO) upon said stack gate prior to said creating said source region and said creating said drain region, wherein additional oxide material is created in said damaged region of said tunnel oxide layer of said stack gate, wherein said performing said RTO prior to said creating said source and drain regions prevents a dopant diffusion into from said source and said drain regions into a channel region.

12. The method as recited in claim 11 , wherein said patterning comprises creating a stack gate upon said semiconductor substrate is less than 0.21 microns (0.21μ) in length.

13. The method as recited in claim 11 , wherein said rapid thermal oxidation process comprises selecting a plurality of process parameters wherein a portion of said tunnel oxide layer retains a uniform profile after said rapid thermal process is performed.

14. The method as recited in claim 13 , wherein said rapid thermal oxidation process comprises exposing said semiconductor structure to a temperature of 1000° C. for a period of time not longer than 20 seconds.

Assignments (10)