Semiconductor memory device provided with error correcting code circuitry
View Patent ↗A semiconductor synchronous dynamic random access memory (SDRAM) device capable of correcting bits having a low error rate in a Pause Refresh Tail distribution and of reducing a data holding current by lengthening a refresh period so that the refresh period exceeds a period for a Pause Refresh real power. The semiconductor memory device is made up of a 16-bit SDRAM having a Hamming Code and including an ECC (Error Correcting Code) circuit made up of an encoding circuit controlled by a first test signal to output a parity bit corresponding to an information bit, a decoding circuit controlled by second test signal to output an error location detecting signal indicating an error bit in codeword, and an error correcting circuit controlled by a third test signal to input an error location detecting signal and to output an error bit in a reverse manner.
1. A semiconductor memory device comprising:
an SDRAM array made up of a plurality of memory cells and having an information bit area wherein information bits are written in and/or read from and a parity bit area wherein parity bits are written in and/or read from, and a redundant circuit to replace error bits contained in at least one of said information bits and said parity bits; and
an error correcting code (ECC) circuit to perform error correcting processing, using a Hamming Code on data including said information bits and said parity bits being written in and/or read from said information bit area and said parity bit area, respectively, in said SDRAM array,
wherein use of redundant correcting processing to correct said error bits using a redundant circuit in said SDRAM array is combined with said error correcting processing using said Hamming Code in said error correcting code (ECC) circuit, and
wherein said error correcting code circuit comprises a plurality of divided error correcting code circuits provided independently of each other for each independent data mask block and controlled by independent data mask signals as external signals.
2. The semiconductor memory device according to claim 1 , wherein, when reading process is performed on said information bit area or said parity bit area, said read data on which said error correcting processing has been performed is output to only an outside of said SDRAM array without being rewritten into said information bit area or said parity area.
3. The semiconductor memory device according to claim 1 , wherein, when a codeword made up of bits is beyond a correcting capability of said error correcting processing using said Hamming Code, said redundant correction processing is performed on said error bits using said redundant circuit.
4. The semiconductor memory device according to claim 1 , wherein said error correcting code (ECC) circuit comprises an encoding circuit to output, by arithmetic operations, said parity bit corresponding to said information bit, a decoding circuit to output an error location detecting signal indicating an error bit out of all bits contained in said codeword, and an error correcting circuit to input said error location detecting signal and to output an error bit in a reverse manner.
5. The semiconductor memory device according to claim 4 , wherein said encoding circuit comprises a syndrome tree in which a plurality of AND circuits to which a first test signal is fed is connected to a plurality of exclusive OR circuits in a manner to provide a specified relationship.
6. The semiconductor memory device according to claim 4 , wherein said decoding circuit comprises a syndrome tree in which a plurality of exclusive OR circuits is connected to one another so that a plurality of bits of said information bits and a plurality of bits of said parity bits are input and a plurality of bits of syndromes is output and decoders to which a plurality of NAND circuits to which a plurality of bits of said syndromes is input and in which a plurality of bits of said error location detecting signals are output and a plurality of AND circuits to which a second test signal is fed are connected to one another in a manner to provide a specified relationship.
7. The semiconductor memory device according to claim 4 , wherein, in said error correcting circuit, a plurality of exclusive OR circuits to which a plurality of bits of said error location detecting signals is input together with a plurality of bits of said information bits and a plurality of bits of said parity bits and a plurality of switches to which a third test signal is fed are connected to one another in a manner to provide a specified relationship so that said error bits are output in a reverse manner.
8. A semiconductor memory device comprising:
an SDRAM array made up of a plurality of memory cells and having an information bit area wherein information bits are written in and/or read from and a parity bit area wherein parity bits are written in and/or read from, and a redundant circuit to replace error bits contained in at least one of said information bits and said parity bits; and
an error correcting code (ECC) circuit to perform error correcting processing, using a Hamming Code whose code length is 72 or less on data including said information bits and said parity bits being written in and/or read from said information bit area and said parity bit area, respectively, in said SDRAM array,
wherein use of redundant correcting processing to correct said error bits using a redundant circuit in said SDRAM array is combined with said error correcting processing using said Hamming Code in said error correcting code (ECC) circuit, and
wherein said error correcting code circuit comprises a plurality of divided error correcting code circuits provided independently of each other for each independent data mask block and controlled by independent data mask signals as external signals.
9. The semiconductor memory device according to claim 8 , wherein, when reading process is performed on said information bit area or said parity bit area, said read data on which said error correcting processing has been performed is output to only an outside of said SDRAM array without being rewritten into said information bit area or said parity area.
10. The semiconductor memory device according to claim 8 , wherein, when a codeword made up of bits is beyond a correcting capability of said error correcting processing using said Hamming Code, said redundant correction processing is performed on said error bits using said redundant circuit.
11. The semiconductor memory device according to claim 8 , wherein said error correcting code (ECC) circuit comprises an encoding circuit to output, by arithmetic operations, said parity bit corresponding to said information bit, a decoding circuit to output an error location detecting signal indicating an error bit out of all bits contained in said codeword, and an error correcting circuit to input said error location detecting signal and to output an error bit in a reverse manner.
12. The semiconductor memory device according to claim 11 , wherein said encoding circuit comprises a syndrome tree in which a plurality of AND circuits to which a first test signal is fed is connected to a plurality of exclusive OR circuits in a manner to provide a specified relationship.
13. The semiconductor memory device according to claim 11 , wherein said decoding circuit comprises a syndrome tree in which a plurality of exclusive OR circuits is connected to one another so that plurality of bits of said information bits and a plurality of bits of said parity bits are input and a plurality of bits of syndromes is output and decoders to which a plurality of NAND circuits to which a plurality of bits of said syndromes is input and in which a plurality of bits of said error location detecting signals are output and a plurality of AND circuits to which a second test signal is fed are connected to one another in a manner to provide a specified relationship.
14. The semiconductor memory device according to claim 11 , wherein said error correcting circuit, a plurality of exclusive OR circuits to which a plurality of bits of said error location detecting signals is input together with a plurality of bits of said ingormation bits and a plurality of bits of said parity bits and a plurality of switches to which a third test signal is fed are connected to one another in a manner to provide a specified relationship so that said error bits are output in a reverse manner.