Flash memory cell having reduced leakage current
View Patent ↗A flash memory cell of the present invention comprises a floating gate, having a charge trapping region and a fin region. A source region and a drain region is formed proximate the floating gate. A control gate is formed above the charge trapping region of the floating gate. The fin region advantageously reduces leakage current, thereby allowing further scaling of the cell.
1. A flash memory cell comprising:
a substrate having a source region, a drain region, and a channel region coupled between said source region and said drain region;
a floating gate, having a charge trapping region and a first fin region, wherein said charge trapping region is coupled to said channel region and said first fin region is coupled to said source region, wherein said first fin region comprises a doped region to reduce leakage current; and
a control gate coupled to said charge trapping region.
2. The flash memory cell according to claim 1 , wherein said first fin region reduces drain to source leakage current.
3. The flash memory cell according to claim 1 , wherein said first fin region increases drain to source read current.
4. The flash memory cell according to claim 1 , wherein said first fin region reduces drain induced barrier reduction.
5. The flash memory cell according to claim 1 , wherein said first fin region reduces barrier scattering.
6. The flash memory cell according to claim 1 , wherein said floating gate further comprises a second fin region, wherein said second fin region is coupled to said drain region.
7. The flash memory cell according to claim 6 , wherein said second fin region reduces drain to source leakage current.
8. The flash memory cell according to claim 6 , wherein said second fin region increases drain to source read current.
9. A floating gate transistor comprising:
a source;
a drain;
a channel disposed between said source and said drain;
a charge trapping region disposed above said channel region;
a first fin disposed adjacent said charge trapping region and above said source, wherein said first fin comprises a doped region to reduce leakage current;
a first isolation layer disposed above said channel and said source and below said charge trapping region and said first fin;
a control gate disposed above said charge trapping region; and
a second isolation layer disposed above said charge trapping region and said first fin and below said control gate.
10. The floating gate transistor according to claim 9 , wherein said first fin comprises p-doped semiconductor.
11. The floating gate transistor according to claim 9 , further comprising:
a second fin disposed adjacent said charge trapping region and above said drain; and said first isolation layer further disposed above said drain and below said second fin.
12. The floating gate transistor according to claim 11 , wherein said second fin comprises p-doped semiconductor.
13. The floating gate transistor according to claim 9 , wherein:
said source comprises n-doped semiconductor;
said drain comprises n-doped semiconductor; and
said channel comprises p-doped semiconductor.
14. The floating gate transistor according to claim 9 , wherein:
said source comprises p-doped semiconductor;
said drain comprises p-doped semiconductor; and
said channel comprises n-doped semiconductor.
15. The floating gate transistor according to claim 9 , wherein:
said first isolation layer comprises a dielectric; and said second isolation layer comprises a dielectric.