Content addressable memory (CAM) devices with dual-function check bit cells that support column redundancy and check bit cells with reduced susceptibility to soft errors
View Patent ↗Content addressable memory (CAM) devices include dual-function check bit cells that can operate as check bit cells to support error detection and correction (EDC) operations or as redundant CAM cells that support column redundancy. Dedicated check bit cells are also provided that have a reduced susceptibility to soft errors relative to adjacent CAM cells. The dedicated check bit cells may also be provided within a global mask cell sub-array to support correction of soft errors within global masks.
1. A content addressable memory (CAM) device, comprising:
a CAM array block having at least one row therein that comprises a plurality of CAM cells and a dual-function check bit cell pair that is configurable as a CAM cell when necessary to account for a defective CAM cell in the at least one row.
2. The CAM device of claim 1 , wherein the at least one row comprises a plurality of dedicated check bit cells that are not configurable as CAM cells.
3. The CAM device of claim 2 , wherein at least some of the dedicated check bit cells are configured to retain parity data.
4. The CAM device of claim 2 , wherein a first dedicated check bit cell in the plurality thereof is configured to be less susceptible to soft errors relative to a check bit cell in the dual-function check bit cell pair by virtue of the fact that latching inverters within the first dedicated check bit cell are larger than latching inverters within the check bit cell in the dual-function check bit cell pair.
5. The CAM device of claim 2 , wherein the at least one row comprises at least one redundant check bit cell.
6. The CAM device of claim 1 , wherein each of the plurality of CAM cells comprises at least one SRAM memory cell having a first pair of inverters therein that define a first latch; wherein the at least one row comprises a dedicated SRAM check bit cell having a second pair of inverters therein that define a second latch; and wherein the second pair of inverters are larger than the first pair of inverters.
7. The CAM device of claim 1 , wherein the at least one row further comprises at least one dedicated check bit cell and at least one flag cell therein, said at least one flag cell configured to designate a valid of invalid status of a respective check bit(s) retained by the at least one dedicated check bit cell.
8. The CAM device of claim 1 , wherein the dual-function check bit cell pair comprises a 4T compare circuit.
9. The CAM device of claim 1 , wherein the CAM cells are static CAM cells.
10. The CAM device of claim 1 , wherein the plurality of CAM cells and the dual-function check bit cell pair are electrically connected to a match line associated with the at least one row.
11. The CAM device of claim 10 , wherein the at least one row comprises at least one dedicated check bit cell that is not electrically connected to the match line.
12. The CAM device of claim 2 , wherein a first dedicated check bit cell in the plurality thereof is configured to be less susceptible to soft errors relative to a check bit cell in the dual-function check bit cell.
13. A content addressable memory (CAM) device, comprising:
a CAM array block having a row therein comprising a plurality of CAM cells, a plurality of dedicated check bit cells and a dual-function check bit cell pair that is configurable as a CAM cell when necessary to account for a defective CAM cell in the row.
14. The CAM device of claim 13 , wherein the row further comprises a redundant check bit cell therein.