Method for fabricating MOS transistors

1. A method for fabricating one or more MOS transistors, the method comprising the steps of:

forming a buffer oxide layer on a semiconductor substrate having an isolation layer;

conducting ion implantations for well formation and field stop formation in an active region of the substrate through the buffer oxide layer;

removing the buffer oxide layer;

forming a sacrificial oxide layer on the semiconductor substrate;

patterning the sacrificial oxide layer to form a trench defining a gate electrode forming region; and

conducting ion implantations for threshold voltage adjustment and punch stop formation in the semiconductor substrate area under the trench.

2. A method for fabricating one or more MOS transistors, the method comprising the steps of:

forming a buffer oxide layer on a semiconductor substrate having an isolation layer;

conducting ion implantations for well formation and field stop formation in an active region of the substrate through the buffer oxide layer;

removing the buffer oxide layer;

forming a sacrificial oxide layer on the semiconductor substrate;

patterning the sacrificial oxide layer to form a trench defining a gate electrode forming region;

conducting ion implantations for threshold voltage adjustment and punch stop formation in the semiconductor substrate area exposed by the trench;

forming a gate oxide layer on the exposed surface of the substrate;

forming a gate electrode layer on the sacrificial oxide layer so as to completely fill the trench;

polishing the gate electrode layer until the surface of the sacrificial oxide layer is exposed, so as to form a gate electrode;

removing the sacrificial oxide layer;

forming an LDD region in the surface of the substrate at both side portions of the gate electrode;

forming spacers on both side walls of the gate electrode; and

forming source/drain regions in the surface of the substrate at both side portions of the gate electrode including the spacers.

3. The method for fabricating MOS transistors as claimed in claim 1 , wherein ion implantation for punch stop formation is conducted only in the semiconductor substrate area under the trench.

4. The method for fabricating MOS transistors as claimed in claim 1 , wherein the sacrificial oxide layer comprises a chemical vapor deposition (CVD) oxide layer.

5. The method for fabricating MOS transistors as claimed in claim 1 , wherein the sacrificial oxide layer has a thickness ranging between 500 Å and 1000 Å.

6. The method for fabricating MOS transistors as claimed in claim 1 , wherein the patterning of the sacrificial oxide layer comprises wet-etching the sacrificial oxide layer.

7. The method for fabricating MOS transistors as claimed in claim 1 , wherein ions implanted for well formation and field stop formation comprise boron, phosphorous or Arsenic.

8. The method for fabricating MOS transistors as claimed in claim 1 , wherein ion implantation for field stop formation is conducted at a sufficient energy to form a barrier below a source/drain junction.

9. The method as claimed in claim 2 , wherein ion implantation for punch stop formation is conducted only in the semiconductor substrate area exposed by the trench.

10. The method as claimed in claim 2 , wherein the sacrificial oxide layer comprises a chemical vapor deposition (CVD)) oxide layer.

11. The method as claimed in claim 2 , wherein the sacrificial layer has a thickness ranging between 500 Å and 1000 Å.

12. The method as claimed in claim 2 , wherein the patterning of the sacrificial oxide layer comprises wet-etching the sacrificial oxide layer.

13. The method as claimed in claim 2 , wherein ions implanted for well formation and field stop formation comprise boron, phosphorous or Arsenic.

14. The method as claimed in claim 2 , wherein ion implantation for field stop formation is conducted at a sufficient energy to form a barrier below a source/drain junction.

15. The method as claimed in claim 2 , wherein said gate electrode layer comprises polysilicon.

16. The method as claimed in claim 1 , wherein the sacrificial oxide layer consists essentially of an oxide layer.

17. The method as claimed in claim 16 , wherein the sacrificial oxide layer has a thickness ranging between 500 Å and 1000 Å.

18. A method for fabricating a MOS transistor, comprising the steps of:

conducting ion implantations for threshold voltage adjustment and punch stop formation in an exposed semiconductor substrate area, said semiconductor substrate having an isolation layer therein and a patterned sacrificial oxide layer thereon, the patterned sacrificial oxide layer having a trench therein (i) defining a gate electrode forming region and (ii) exposing said exposed semiconductor substrate area;

forming a gate electrode in the trench;

removing the patterned sacrificial oxide layer;

forming an LDD region in the substrate at side portions of the gate electrode;

forming spacers on side walls of the gate electrode; and

forming source/drain regions in areas of the substrate not covered by the gate electrode and the spacers.

19. The method as claimed in claim 18 , wherein the sacrificial oxide layer consists essentially of an oxide layer.

20. The method as claimed in claim 18 , wherein the sacrificial layer comprises a chemical vapor deposition (CVD) oxide layer.