Semiconductor integrated circuit device having deposited layer for gate insulation
View Patent ↗A method for manufacturing a semiconductor integrated circuit device including a first field effect transistor having a gate insulating film formed over a first element forming region of a main surface of a semiconductor substrate; and a second field effect transistor having a gate insulating film formed over a second element forming region of the main surface of the semiconductor substrate and made thinner than the gate insulating film of the first field effect transistor. The method comprises the steps of forming a thermally oxidized film over a first element forming region and a second element forming region of the main surface of the semiconductor substrate; forming a deposited film over the main surface of the semiconductor substrate including said thermally oxidized film; removing the deposited film and said thermally oxidized film from over the second element forming region; and forming a thermally oxidized film over the second element forming region to form a gate insulating film individually over the first element forming region and the second element forming region.
1. A semiconductor integrated circuit device, comprising:
a first MISFET having a first gate insulating film formed over a first element forming region of a main surface of a semiconductor substrate and a first gate electrode formed over said first gate insulating film; and
a second MISFET having a second gate insulating film formed over a second element forming region of said main surface of said semiconductor substrate and a second gate electrode formed over said second gate insulating film,
said second gate insulating film being thinner than said first gate insulating film,
wherein said first gate insulating film includes a thermally oxidized film and a deposited film formed over said thermally oxidized film and having a thickness greater than that of said thermally oxidized film,
wherein said second gate insulating film includes a thermally oxidized film,
wherein a thickness of said thermally oxidized film of said first gate insulating film is thinner than that of said thermally oxidized film of said second gate insulating film,
wherein said first element forming region and said second element forming region are individually isolated by an element isolation region,
wherein said element isolation region is formed by forming grooves in said substrate, depositing an insulating film over said grooves by a vapor deposition method, and polishing said insulating film so as to fill said insulating film in said grooves, and
wherein said deposited film extends over said element isolation region such that an edge portion of said first gate electrode is formed over said deposited film at a portion of said deposited film positioned over said element isolation region.
2. A semiconductor integrated circuit device according to claim 1 , wherein an etching rate of said insulating film filled in said groove is lower than that of said thermally oxidized film.
3. A semiconductor integrated circuit device according to claim 1 , wherein said deposited film is formed by a vapor deposition method.
4. A semiconductor integrated circuit device according to claim 3 , wherein said vapor deposition method is a chemical vapor deposition method.
5. A semiconductor integrated circuit device according to claim 1 , wherein said element isolation region is an insulating region having a thickness greater than that of said first gate insulating film.
6. A semiconductor integrated circuit device according to claim 5 , wherein said insulating film is integrally formed with an element isolation film defining a first MISFET forming region, and wherein an etching rate of said insulating film filled in said groove is lower than that of a thermally oxidized film.