IP Library Granted Patent US 6,858,930
Granted Patent B2
US 6,858,930 · App. 10/638,772 · Granted Feb 22, 2005

Multi chip module

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 6,858,930
App. No.
10/638,772
Granted
Feb 22, 2005
Kind
B2
Abstract

A multi chip package, which includes a package substrate having a first side and an opposing second side. The first side is for receiving package electrical connections. Integrated circuits are electrically connected and structurally connected by their first sides to the second side of the package substrate. Heat spreaders are disposed adjacent the second side of the integrated circuits, where one each of the heat spreaders is associated with one each of the integrated circuits. A single stiffener having a first side and an opposing second side covers all of the integrated circuits and heat spreaders, where the first side of the stiffener is disposed adjacent the second side of the heat spreaders.

Claims (37)

1. A multi chip package, comprising:

a package substrate having a first side and an opposing second side, the first side for receiving package electrical connections,

integrated circuits each having a first side and an opposing second side, the first side of each of the integrated circuits electrically connected and structurally connected to the second side of the package substrate,

heat spreaders each having a first side and an opposing second side, the first side of each of the heat spreaders disposed adjacent the second side of the integrated circuits, where one each of the heat spreaders is associated with one each of the integrated circuits,

a single stiffener having a first side and an opposing second side, the stiffener covering all of the integrated circuits and heat spreaders, the first side of the stiffener disposed adjacent the second side of the heat spreaders, and

discrete components electrically connected to the second side of the package substrate and coplanar with the integrated circuits.

2. The multi chip package of claim 1 , further comprising ball grid array package electrical connections disposed on the first side of the package substrate.

3. The multi chip package of claim 1 , wherein the heat spreaders are formed of copper.

4. The multi chip package of claim 1 , wherein the stiffener is formed of copper.

5. A multi chip package, comprising:

a package substrate having a first side and an opposing second side, the first side for receiving package electrical connections,

integrated circuits each having a first side and an opposing second side, the first side of each of the integrated circuits electrically connected and structurally connected to the second side of the package substrate,

heat spreaders each having a first side and an opposing second side, the first side of each of the heat spreaders disposed adjacent the second side of the integrated circuits, where one each of the heat spreaders is associated with one each of the integrated circuits,

a thermal epoxy disposed between the second side of each of the integrated circuits and the first side of each of the heat spreaders, the thermal epoxy for conducting thermal energy to the heat spreaders and away from the integrated circuits, and

a single stiffener having a first side and an opposing second side, the stiffener covering all of the integrated circuits and heat spreaders, the first side of the stiffener disposed adjacent the second side of the heat spreaders.

6. The multi chip package of claim 5 , further comprising ball grid array package electrical connections disposed on the first side of the package substrate.

7. The multi chip package of claim 5 , wherein the heat spreaders are formed of copper.

8. The multi chip package of claim 5 , wherein the stiffener is formed of copper.

9. A multi chip package, comprising:

a package substrate having a first side and an opposing second side, the first side for receiving package electrical connections,

integrated circuits each having a first side and an opposing second side, the first side of each of the integrated circuits electrically connected and structurally connected to the second side of the package substrate,

heat spreaders each having a first side and an opposing second side, the first side of each of the heat spreaders disposed adjacent the second side of the integrated circuits, where one each of the heat spreaders is associated with one each of the integrated circuits,

a single stiffener having a first side and an opposing second side, the stiffener covering all of the integrated circuits and heat spreaders, the first side of the stiffener disposed adjacent the second side of the heat spreaders, and

a thermal epoxy disposed between the second side of each of the heat spreaders and the first side of the stiffener, the thermal epoxy for conducting thermal energy to the stiffener and away from the heat spreaders.

10. The multi chip package of claim 9 , further comprising ball grid array package electrical connections disposed on the first side of the package substrate.

11. The multi chip package of claim 9 , wherein the heat spreaders are formed of copper.

12. The multi chip package of claim 9 , wherein the stiffener is formed of copper.

13. A multi chip package, comprising:

a package substrate having a first side and an opposing second side, the first side for receiving package electrical connections,

integrated circuits each having a first side and an opposing second side, the first side of each of the integrated circuits electrically connected and structurally connected to the second side of the package substrate,

heat spreaders each having a first side and an opposing second side, the first side of each of the heat spreaders disposed adjacent the second side of the integrated circuits, where one each of the heat spreaders is associated with one each of the integrated circuits, and

a single stiffener having a first side and an opposing second side, the stiffener covering some but not all of the integrated circuits and heat spreaders, the first side of the stiffener disposed adjacent the second side of the heat spreaders.

14. The multi chip package of claim 13 , further comprising a thermal epoxy disposed between the second side of each of the integrated circuits and the first side of each of the heat spreaders, the thermal epoxy for conducting thermal energy to the heat spreaders and away from the integrated circuits.

15. The multi chip package of claim 13 , further comprising a thermal epoxy disposed between the second side of each of the heat spreaders and the first side of the stiffener, the thermal epoxy for conducting thermal energy to the stiffener and away from the heat spreaders.

16. The multi chip package of claim 13 , further comprising discrete components electrically connected to the second side of the package substrate and coplanar with the integrated circuits.

17. The multi chip package of claim 13 , further comprising bail grid array package electrical connections disposed on the first side of the package substrate.

18. The multi chip package of claim 13 , wherein the heat spreaders are formed of copper.

Assignments (9)
RELEASE OF SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 059723/0382 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 3, 2020
From: BELL SEMICONDUCTOR, LLC
To: BELL NORTHERN RESEARCH, LLC
Reel/Frame 051703/0433 →
SECURITY INTEREST Recorded Feb 1, 2018
From: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
To: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
Reel/Frame 045216/0020 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044886/0766 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →