Static timing analysis approach for multi-clock domain designs
View Patent ↗A method for analyzing a circuit design is disclosed. The method generally includes the steps of (A) determining a plurality of paths from a first clock at a first location to a plurality of second clocks at a plurality of second locations in the circuit design, (B) calculating a plurality of delays along the paths and (C) calculating a plurality of latencies with respect to the first clock for the second clocks using the delays.
1. A method for analyzing a circuit design, comprising the steps of:
(A) determining a plurality of paths from a first clock at a first location to a plurality of second clocks at a plurality of second locations in said circuit design, wherein said second clocks are derived from said first clock;
(B) calculating a plurality of delays along said paths wherein at least two of said delays are associated with each of said paths; and
(C) calculating a plurality of latencies with respect to said first clock for said second clocks using said delays.
2. The method according to claim 1 , further comprising the step of:
calculating a particular latency between two of said second clocks as a difference of two of said latencies with respect to said first clock.
3. The method according to claim 1 , wherein at least one of said paths is a longest physical distance from said first location to one of said second locations.
4. The method according to claim 1 , wherein each of said delays comprise both a rise delay and an associated fall delay along a respective portion among a plurality of portions in each of said paths.
5. The method according to claim 4 , wherein at least one of said rise delays is different than said associated fall delay through said respective portion.
6. The method according to claim 1 , wherein step (C) comprises the sub-step of:
calculating a plurality of rise latencies of said latencies for said second clocks by summing a plurality of rise delays of said delays along said paths.
7. The method according to claim 1 , wherein step (C) further comprises the sub-steps of:
calculating a plurality of fall latencies of said latencies for said second clocks by summing a plurality of fall delays of said delays along said paths.
8. The method according to claim 1 , further comprising the step of:
calculating a fall delay of said first clock from a plurality of parameters.
9. The method according to claim 8 , wherein said parameters comprise a period, a duty cycle and a rise delay.
10. The method according to claim 1 , further comprising the step of:
calculating a plurality of pulse widths, one of said pulse widths for each of said second clocks using (i) a plurality of rise delays of said delays and (ii) a plurality of fall delays of said delays.
11. The method according to claim 1 , further comprising the step of:
generating a plurality of definitions for said second clocks based on both (i) said latencies of said second clocks and (ii) said delays along said paths.
12. A storage medium for use in a computer for analysis of a circuit design, the storage medium recording a computer program that is readable and executable by the computer, the computer program comprising:
(A) determining a plurality of paths from a first clock at a first location to a plurality of second clocks at a plurality of second locations in said circuit design with said computer, wherein said second clocks are derived from said first clock;
(B) calculating a plurality of delays along said paths with said computer, wherein at least two of said delays are associated with each of said paths; and
(C) calculating a plurality of latencies with respect to said first clock for said second clocks using said delays with said computer.
13. The storage medium according to claim 12 , further comprising the step of:
calculating a particular latency between two of said second clocks as a difference of two of said latencies with respect to said first clock.
14. The storage medium according to claim 12 , wherein step (C) comprises the sub-step of:
calculating a plurality of rise latencies of said latencies for said second clocks by summing a plurality of rise delays of said delays along said paths.
15. The storage medium according to claim 12 , wherein step (C) comprises the sub-step of:
calculating a plurality of fall latencies of said latencies for said second clocks by summing a plurality of fall delays of said delays along said paths.
16. The storage medium according to claim 12 , further comprising the step of:
calculating a first pulse width of said first clock using a period, a duty cycle and a rise delay.
17. The storage medium according to claim 12 , wherein step (A) further comprises the sub-step of:
generating a path file storing said paths by processing a layout of said circuit design read from a layout database.
18. The storage medium according to claim 12 , wherein step (B) further comprises the sub-step of:
generating a delay file storing said delays.
19. An apparatus comprising:
a clock file;
a user input file;
a first tool configured to (i) read at least one parameter for a first clock of a circuit design from said user input file, (ii) generate a plurality of definitions for a plurality of second clocks from said circuit design and said first clock and (iii) store said definitions in said clock file, wherein said second clocks are derived from said first clock; and
a second tool configured to (i) read said definitions from said clock file and (ii) generate a timing report for said second clocks by performing a static timing analysis for said circuit design based upon said definitions.
20. The apparatus according to claim 19 , wherein said first tool comprises:
a path tool configured to (i) read layout information from a layout database for said circuit design and (ii) generate a path file storing a plurality of paths for said second clocks in response to said layout information.
21. The apparatus according to claim 20 , wherein said layout database comprises at least one of a pre-layout database and a post-layout database for said circuit design.
22. The apparatus according to claim 19 , wherein said first tool further comprises:
a delay tool configured to (i) read path information for a plurality of paths from a path file, (ii) generate a delay file storing a plurality of delay values along said paths based on said path information and (iii) generate a latency file storing a plurality of latency values for said second clocks based on said path information.
23. The apparatus according to claim 19 , wherein said first tool further comprises:
a clock definition tool configured to (i) read a plurality of delay values from a delay file, (ii) read a plurality of latency values from a latency file and (iii) generate said definitions based upon both said latency values and said delay values.
24. The apparatus according to claim 19 , wherein said circuit design is at least a portion of a code division multiple access circuit design.
25. An apparatus comprising:
a path tool configured to generate a path file storing a plurality of paths for a plurality of clocks in response to both (i) at least one parameter for a first of said clocks and (ii) a layout database for a circuit design;
a delay tool configured to generate a delay file storing a plurality of delay values along said paths;
a clock definition tool configured to generate a plurality of definitions for said clocks based upon said delay values; and
a static timing analysis tool configured to generate a timing report for said clocks by performing a static timing analysis for said circuit design based upon said definitions.
26. The apparatus according to claim 25 , wherein said delay tool is further configured to generate a latency file storing a plurality of latency values for said clocks.
27. The apparatus according to claim 26 , wherein said clock definition tool is further configured to generate said definitions for said clocks in further response to said latency values.