Multilevel semiconductor memory, write/read method thereto/therefrom and storage medium storing write/read program
View Patent ↗A disclosed semiconductor memory device includes multilevel memory cells in which data in the cells is arranged according to a coding method that allows error correction. One disclosed device has multilevel memory cells arranged so as to correspond to a physical address space, each cell storing 2 n levels of data, each expressed by n (n≧2) number of bits (X 1 , X 2 , Xn). When an input logical address is converted into a physical address, a determination is made whether the logical address space matches the physical address space. If there is not a match, the most significant bit X 1 is specified once using a reference value, and the specified bit is output from one of the cells corresponding to the physical address. If there is not match, the bits (X 2 , . . . , Xn) are specified by an n—time specifying operation using maximum n number of different reference values.
1. A method of reading n (n≧2) number of bits (X 1 , X 2 , . . . , Xn) from a plurality of multilevel memory cells arranged so as to correspond to a physical address space, each cell having at least one transistor, each cell storing 2 n levels of data each expressed by the bits (X 1 , X 2 , . . . , and Xn), comprising the steps of:
converting a logical address into a physical address included in the physical address space;
judging whether a logical address space including the logical address matches the physical address space;
specifying the most significant bit X 1 by applying a predetermined reference voltage to a gate of the transistor to determine whether a current flows between a source and a drain of the transistor when the logical address space matches the physical address space; and
outputting the specified bit from one of the cells corresponding to the physical address.
2. The method according to claim 1 further comprises the step of specifying the bits (X 1 , X 2 , . . . , Xn) by applying maximum n number of different reference voltages to the gate of the transistor at a specific voltage applying order until a current flows between the source and the drain when judged that the logical address space does not match the physical address space.
3. A computer readable medium storing program code for causing a computer to read n (n≧2) number of bits (X 1 , X 2 , . . . , Xn) from a plurality of multilevel memory cells arranged so as to correspond to a physical address space, each cell having at least one transistor, each cell storing 2 n levels of data each expressed by the bits (X 1 , X 2 , . . . , Xn), comprising:
first program code means for converting a logical address into a physical address included in the physical address space;
second program code means for judging whether a logical address space including the logical address matches the physical address space;
third program code means for specifying the most significant bit X 1 by applying a reference voltage to a gate of the transistor when the logical address space matches the physical address space to determine whether a current flows between a source and a drain of the transistor; and
fourth program code means for outputting the specified bit from one of the cells corresponding to the physical address.
4. The computer readable medium according to claim 3 further comprising the program code means for specifying the bits (X 1 , X 2 , . . . , Xn) by applying maximum n number of different reference voltages to the gate of the transistor at a specific voltage applying order until a current flows between the source and the drain when judged that the logical address space does not match the physical address space.