IP Library › Granted Patent US 6,958,527
Granted Patent B2
US 6,958,527 · App. 10/654,424 · Granted Oct 25, 2005

Wiring board having interconnect pattern with land, and semiconductor device, circuit board, and electronic equipment incorporating the same

Assignee: Seiko Epson Corporation
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Quick Facts
Patent No.
US 6,958,527
App. No.
10/654,424
Granted
Oct 25, 2005
Kind
B2
Abstract

A wiring board includes a substrate, and an interconnect pattern which is formed on the substrate and includes a land. A penetration hole, which exposes the substrate, is formed in the land. The penetration hole is formed in a region along a periphery of the land.

Claims (25)

1. A wiring board comprising:

a substrate;

an interconnect pattern which is formed on the substrate and includes a land having a penetration hole; and

a resist layer covering at least the penetration hole, the penetration hole being formed in a region along a periphery of the land.

2. The wiring board as defined in claim 1 , wherein a planar shape of the land is approximately circular.

3. The wiring board as defined in claim 1 , wherein the penetration hole is an elongated hole exposing the substrate.

4. The wiring board as defined in claim 3 , wherein the penetration hole is the elongated hole which is longer in a direction along the periphery of the land than in a direction intersecting the periphery of the land at right angles.

5. The wiring board as defined in claim 1 , wherein a plurality of the penetration holes are formed in the land.

6. The wiring board as defined in claim 5 , wherein the plurality of penetration holes are arranged in a region along the periphery of the land.

7. The wiring board as defined in claim 5 , wherein the plurality of penetration holes are disposed so that distance between the adjacent penetration holes is approximately the same.

8. The wiring board as defined in claim 1 , further comprising:

the resist layer being formed on a surface of the substrate on which the interconnect pattern is formed and includes an opening which exposes at least a part of the land.

9. The wiring board as defined in claim 8 , wherein a planar shape of the opening of the resist layer is approximately circular.

10. The wiring board as defined in claim 8 , wherein the resist layer covers at least a part of the penetration hole.

11. The wiring board as defined in claim 8 ,

wherein the resist layer covers the penetration hole, and

wherein part of an edge of the penetration hole is in contact with an edge of the opening of the resist layer.

12. The wiring board as defined in claim 1 , which is formed as an interposer.

13. The wiring board as defined in claim 1 , which is formed as a motherboard.

14. A semiconductor device comprising:

the wiring board as defined in claim 1 , and

a semiconductor chip which is electrically connected with the interconnect pattern.

15. The semiconductor device as defined in claim 14 , further comprising an external terminal formed on the land.

16. A circuit board on which the semiconductor device as defined in claim 14 is mounted.

17. Electronic equipment comprising the semiconductor device as defined in claim 14 .

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 11, 2003
From: HANAOKA, TERUNAO
To: SEIKO EPSON CORPORATION
Reel/Frame 014189/0781 →
Priority Claims (1)
JP 2002-298324 · Oct 11, 2002 · national
Continuity (1)
Related Publication 20040075177A1 · Apr 22, 2004