Flash memory with high-K dielectric material between substrate and gate
View Patent ↗A flash memory cell and a method of forming the same are described. The flash memory cell may include a substrate having a source and a drain, a gate element, and a dielectric layer between the substrate and the gate element. The dielectric layer includes a dielectric material having a dielectric constant that is greater than that of silicon dioxide.
1. A flash memory cell comprising:
a substrate comprising a source and a drain;
a silicon dioxide layer adjoining said substrate;
a dielectric layer adjoining said silicon dioxide layer, said dielectric layer comprising a dielectric material having a dielectric constant greater than that of silicon dioxide, wherein said dielectric material comprises a metal oxide;
a polysilicon floating gate adjoining said dielectric layer;
an oxide-nitride-oxide (ONO) layer adjoining said floating gate; and
a control gate adjoining said ONO layer, wherein said substrate, said silicon dioxide layer, said dielectric layer, said floating gate, said ONO layer and said control gate are arranged in a laminate structure, wherein said silicon dioxide layer is sandwiched between said substrate and said dielectric layer, wherein said dielectric layer is sandwiched between said silicon dioxide layer and said floating gate, and wherein said ONO layer is sandwiched between said floating gate and said control gate.
2. The flash memory cell of claim 1 wherein said dielectric layer comprises a composite of said metal oxide and a material selected from the group consisting of silicon dioxide, silicon oxynitride and silicon oxynitrate.
3. A flash memory array comprising memory cells, wherein a memory cell comprises:
a substrate comprising a source and a drain;
a tunnel oxide layer adjoining said substrate, said tunnel oxide layer comprising a dielectric material having a dielectric constant greater than that of silicon dioxide, wherein said dielectric material comprises a metal oxide;
a first layer comprising a silicon material;
a polysilicon floating gate adjoining said first layer;
an oxide-nitride-oxide (ONO) layer adjoining said floating gate; and
a control gate adjoining said ONO layer, wherein said substrate, said tunnel oxide layer, said first layer, said floating gate, said ONO layer and said control gate are arranged in a laminate structure, wherein said tunnel oxide layer is sandwiched between said substrate and said first layer, wherein said first layer is sandwiched between said tunnel oxide layer and said floating gate, and wherein said ONO layer is sandwiched between said floating gate and said control gate.
4. The flash memory array of claim 3 wherein said silicon material is selected from the group consisting of silicon dioxide, silicon oxynitride and silicon oxynitrate.