IP Library Granted Patent US 7,093,356
Granted Patent B2
US 7,093,356 · App. 10/661,530 · Granted Aug 22, 2006

Method for producing wiring substrate

Assignee: Shinko Electric Industries Co., Ltd.
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Quick Facts
Patent No.
US 7,093,356
App. No.
10/661,530
Granted
Aug 22, 2006
Kind
B2
Abstract

A wiring substrate with bumps protruding from a surface of the substrate covers one side of a metallic base with an electrical insulating film thereon, having open holes exposing the base, etching the base through the open holes to form concavities in the base, electroplating the interior faces of the concavities to form a barrier metal film thereon filling the concavities with a bump material by electroplating, and forming a barrler layer on the bump material in each concavity. A stack of wiring patterns is formed on the insulating film, adjacent wiring patterns being separated by a respective intervening insulating layer and being electrically connected to each other through vias in the intervening insulating layer, and to the bump material filled in the concavities. Thereafter, the base and barrier metal film are removed.

Claims (20)

1. A method for producing a wiring substrate provided with bumps protruding from a surface of the substrate, the method comprising:

covering one side of a metallic base with an electrical insulating film and forming open holes in the insulating film so as to expose, at the bottoms thereof, the base;

etching the base using the insulating film, having the open holes formed therein as a mask, to form concavities in the base;

electroplating the interior face of each of the concavities, using the base as a plating power supply layer, with a first metal material, different from the material of the base, to form a barrier metal film on the interior face of each of the concavities;

completely filling the concavities with a second, bump metal material different from said first metal material, by electroplating, using the base as a plating power supply layer;

forming a barrier layer of a third metal material, different from said second metal material, on the surface of the bump material in each concavity, using the base as a plating power supply layer;

forming a stack of a predetermined number of wiring patterns on the insulating film, the adjacent wiring patterns in the stack being separated from each other by an intervening insulating layer and being electrically connected to each other through vias formed in the intervening insulating layer and to the bump material in the concavities; and

removing the base from the stack of wiring patterns having bumps, each bump having the barrier metal film thereon, and removing the barrier metal film from each of the bumps, thereby producing the wiring substrate.

2. The method of claim 1 , wherein a metallic foil is used as the base, of a size permitting simultaneous production of a plurality of wiring substrates.

3. The method of claim 1 , wherein two metallic bases laminated by joining them by adhering the peripheries thereof are used, and the opposed sides of the laminate are covered with the electrical insulating film.

4. The method of claim 1 , wherein the open holes are formed in the insulating film so as to have tapered interior faces providing a larger diameter at the opening side rather than at the bottom exposing the base.

5. The method of claim 1 , wherein the etching used to etch the base for the formation of the concavities is isotropic, and wherein each of the concavities is formed to have a diameter at the interface with the insulating film, which is larger than the bottom diameter of the hole provided in the insulating film.

6. The method of claim 1 , wherein the concavities are filled with the material for the bump in such a manner that the material fully fills the concavity, and partially protrudes into the open hole in the insulating film.

7. The method of claim 1 , wherein the base is made of copper.

8. The method of claim 7 , wherein the base is a foil of copper.

9. The method of claim 1 , wherein the base is removed by etching.

10. The method of claim 9 , wherein the bumps are formed of solder.

11. The method of claim 1 , wherein the bumps are formed of solder or gold.

12. The method of claim 1 , wherein the barrier metal film is formed of nickel or cobalt.

13. The method of claim 1 , wherein the barrier layer, on the surface of the bump material filled in each concavity, is formed of nickel.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 15, 2003
From: IMAFUJI, KEI; KODAIRA, TADASHI; CHINO, TAKESHI; NAKAMURA, JYUNICHI; ABE, MIWA
To: SHINKO ELECTRIC INDUSTRIES CO., LTD.
Reel/Frame 014502/0171 →
Priority Claims (1)
JP 2002-269962 · Sep 17, 2002 · national
Continuity (1)
Related Publication 20040060174A1 · Apr 1, 2004