Current mirror compensation using channel length modulation
View Patent ↗A current compensation circuit for use with a current mirror circuit is disclosed. The current mirror circuit has a current path defined by a first programmable current mirror stage driving a first fanout current mirror stage. The first programmable current mirror stage includes at least one transistor with a channel length exhibiting a first channel length modulation factor λ 1 . The first fanout current mirror stage connects to a supply voltage source. The current compensation circuit comprises a supply voltage current mirror coupled to the supply voltage source and has a current output coupled to the current path. The compensation circuit further includes a second programmable current mirror coupled in series to the supply voltage current mirror and including at least one transistor with a channel length exhibiting a channel length modulation factor λ 2 . The second channel length modulation factor λ 2 is larger than the first channel length modulation factor λ 1 . As a result, the first programmable current mirror and the second programmable current mirror cooperate to maintain a bias current through the first fanout current mirror stage substantially independent of changes in the supply voltage.
1. A circuit comprising:
a supply voltage current minor configured to be coupled to a supply voltage source, and comprising a current output configured to be coupled to a node; the node coupling a fanout current mirror and a first programmable current minor, the first programmable mirror having a first transistor having a first channel length modulation factor λ 1 ; and
a second programmable current mirror coupled to the supply voltage current mirror and comprising a second transistor having a second channel length modulation factor λ 2 , the second channel length modulation factor λ 2 being larger than the first channel length modulation factor λ 1 , the second programmable current mirror being configured to maintain, with the first programmable current mirror, a bias current through the fanout current mirror substantially independent of voltage changes in the supply voltage source.
2. The circuit of claim 1 wherein the first programmable current mirror comprises a parallel array of programmable transistors for defining a predetermined range of current.
3. The circuit of claim 1 wherein the circuit is formed on a single integrated circuit device.
4. The circuit of claim 3 wherein the circuit is formed using complementary metal-oxide- semiconductor technology.
5. A method for compensating for supply-voltage-induced changes to a desired current through a fanout current mirror, the method comprising:
detecting changes in the voltage from a supply voltage source;
generating a compensation current to a current path node, the compensation current representative of the voltage changes in the supply voltage source, the compensation current based on the channel length modulation factor λ 2 of a second programmable current source; and
sinking current from the current path node with a first programmable current source having a first channel length modulation factor λ 1 , λ 1 being less than λ 2 , wherein the level of current sunk corresponds to the difference between the compensation current and the desired current through the fanout current mirror.
6. A circuit, comprising:
a current mirror circuit, the current mirror circuit comprising:
a first programmable current mirror and a fanout current mirror coupled to the first programmable current mirror by a node, the first programmable current mirror comprising a first transistor having a first channel length modulation factor λ 1 , the fanout current mirror coupled to a supply voltage source, and
a current compensation circuit; the current compensation circuit comprising:
a supply voltage current mirror coupled to the supply voltage source and comprising a current output coupled to the node; and
a second programmable current mirror coupled to the supply voltage current mirror comprising a second transistor with a second channel length modulation factor λ 2 , the second channel length modulation factor λ 2 being larger than the first channel length modulation factor λ 1 , the first programmable current mirror and the second programmable current mirror cooperating to maintain a bias current through the fanout current mirror substantially independent of voltage changes in the supply voltage source.
7. The circuit of claim 6 wherein the first programmable current mirror comprises a parallel array of programmable transistors for defining a predetermined range of current.
8. The circuit of claim 6 wherein the second programmable current mirror comprises a parallel array of programmable transistors for defining a predetermined range of current.
9. The circuit of claim 6 wherein the circuit is formed on a single integrated circuit device.
10. The circuit according to claim 6 wherein the circuit is formed using a complementary metal-oxide-semiconductor.