Integrated resistive elements with silicidation protection
View Patent ↗In a process for the fabrication of integrated resistive elements with protection from silicidation, at least one active area ( 15 ) is delimited in a semiconductor wafer ( 10 ). At least one resistive region ( 21 ) having a pre-determined resistivity is then formed in the active area ( 15 ). Prior to forming the resistive region ( 21 ), however, a delimitation structure ( 20 ) for delimiting the resistive region ( 21 ) is obtained on top of the active area ( 15 ). Subsequently, protective elements ( 25 ) are obtained which extend within the delimitation structure ( 20 ) and coat the resistive region ( 21 ).
1. A semiconductor wafer comprising:
at least one active area;
at least one discrete resistor having a resistive region obtained within said active area, the discrete resistor having first and second ends to which metal contacts are formed;
a delimitation structure set on top of said active area as an ion implantation mask to delimit a size and shape of ion implantation which forms said resistive region, the delimitation structure defining a width of the discrete resistor between the first and second ends; and
a silicide layer formed over the delimitation structure which does not electrically contact the resistor region.
2. The wafer according to claim 1 , wherein said delimitation structure is made of a material used in the semiconductor industry.
3. The wafer according to claim 2 , wherein said delimitation structure is made of a material selected from a group consisting of a dielectric, a semiconductor and a metal.
4. The wafer according to claim 2 , wherein said delimitation structure is made of polysilicon.
5. The wafer according to claim 1 , further comprising a protective element which extends within said delimitation structure and coats said resistive region.
6. The wafer according to claim 5 , wherein said protective element is made of a dielectric material.
7. An integrated device comprising:
a semiconductor substrate;
at least one active area on the semiconductor substrate;
at least one resistor region within said active area, the resistor region having first and second ends to which metal contacts are formed;
a delimitation structure set on top of said active area as an ion implantation mask to delimit a size and shape of ion implantation which forms said resistor region in the semiconductor substrate, the delimitation structure defining a width of the resistor region between the first and second ends; and
a suicide layer formed over the delimitation structure which does not electrically contact the resistor region.
8. The integrated device according to claim 7 , wherein said delimitation structure is made of a material used in the semiconductor industry.
9. The integrated device according to claim 8 , wherein said delimitation structure is made of a material selected from a group consisting of a dielectric, a semiconductor and a metal.
10. The integrated device according to claim 8 , wherein said delimitation structure is made of polysilicon.
11. The integrated device according claim 7 , further comprising a protective element which extends within said delimitation structure and coats said resistor region.
12. The integrated device according to claim 11 , wherein said protective element is made of a dielectric material.
13. An integrated circuit, comprising:
a substrate including an active region;
a discrete resistor formed within the active region of the substrate, the discrete resistor having first and second ends to which metal contacts are formed;
a delimiter structure formed over the substrate and defining a mask used for ion implantation, but not comprising a transistor gate structure of the integrated circuit, to form and define a size and shape of the discrete resistor;
a spacer extending between the delimiter structure to cover the discrete resistor formed in the active region but not cover a top surface of the delimiter structure; and
a silicided layer formed on the delimiter structure without being in electrical contact with the metal contacts of the resistor.
14. An integrated resistive element having protection from silicidation, comprising:
at least one active area in a semiconductor substrate;
at least one resistive region having a pre-set resistiVity in said active area;
a silicided delimitation structure on top of said active area that delimits a width of said resistive region but is not in electrical contact with the resistive region;
a pair of electrical metal contacts positioned at opposite ends of a length of the resistive region; and
a protective structure which protects said resistive region from salicidation, extends within said delimitation structure and covers said resistive region.
15. The element according to claim 14 , wherein said protective structure is made of a material selected from the group consisting of: silicon dioxide, silicon nitride, and silicon oxynitride.
16. The element according to claim 14 , wherein said delimitation structure is made of polysilicon.
17. An integrated circuit, comprising:
an active area defined in a semiconductor substrate;
a resistive region having a pre-set resistivity formed in the active area;
a polysilicon structure, which is not a transistor gate structure of the integrated circuit, defining a mask which delimits a width of ion implantation which forms the resistive region;
a protective layer over the resistive region between the polysilicon structure; and
a silicided layer formed on the polysilicon structure without affecting the pre-set resistivity in the active area and which does not electrically make contact with the resistive region.
18. The circuit according to claim 17 , wherein the protective layer is made of a material selected from the group consisting of: silicon dioxide, silicon nitride, and silicon oxynitride.