Patent Assignment
Reel/Frame 029186/0761
Assignment of Assignor's Interest
Recorded: 2012-10-24
Pages: 134
Assignor
STMICROELECTRONICS S.R.L.
Executed: 2008-02-06
Assignee
MICRON TECHNOLOGY, INC.
8000 S. FEDERAL WAY, BOISE, IDAHO, 83707
Covered Properties
(66)
Row Decoder for a Flash-Eeprom Memory Device with the Possibility of Selective Erasing of a Sub-Group of Rows of a Sector
Patent:
6,122,200 →
Application:
09/200,002 →
Device and Method for Reading Nonvolatile Memory Cells
Patent:
6,181,602 →
Application:
09/322,460 →
Line Decoder for a Low Supply Voltage Memory Device
Patent:
6,111,809 →
Application:
09/324,087 →
Method for Manufacturing Electronic Devices Having Hv Transistors and Lv Transistors with Salicided Junctions
Patent:
6,251,728 →
Application:
09/359,923 →
Method for Manufacturing Electronic Devices Comprising Non-Volatile Memory Cells and Lv Transistors with Salicided Junctions
Patent:
6,281,077 →
Application:
09/392,937 →
Method for Manufacturing Electronic Devices, Comprising Non-Salicided Non-Volatile Memory Cells, Non-Salicided Hv Transistors, and Lv Transistors with Salicided Junctions with Few Masks
Patent:
6,274,411 →
Application:
09/469,849 →
Method for reading a multilevel nonvolatile memory and multilevel nonvolatile memory
Patent:
6,301,149 →
Application:
09/513,598 →
Flash compatible EEPROM
Patent:
6,222,775 →
Application:
09/599,356 →
Single Supply Voltage Nonvolatile Memory Device with Row Decoding
Patent:
6,373,780 →
Application:
09/627,273 →
Method for Programming Multi-Level Non-Volatile Memories by Controlling the Gate Voltage
Patent:
6,366,496 →
Application:
09/631,187 →
Memory test method and nonvolatile memory with low error masking probability
Patent:
6,282,134 →
Application:
09/670,471 →
Method for Controlled Soft Programming of Non-Volatile Memory Cells, in Particular of the Flash Eeprom and Eprom Type
Patent:
6,381,177 →
Application:
09/699,309 →
Process for Manufacturing Electronic Devices Comprising High Voltage Mos Transistors, and Electronic Device Thus Obtained
Patent:
6,501,147 →
Application:
09/713,144 →
Process for Manufacturing Electronic Devices Comprising Nonvolatile Memory Cells of Reduced Dimensions
Patent:
6,509,222 →
Application:
09/718,971 →
Atd Generation in a Synchronous Memory
Interleaved Data Path and Output Management Architecture for an Interleaved Memory and Load Pulser Circuit for Outputting the Read Data
String Programmable Nonvolatile Memory with nor Architecture
Direct-Comparison Reading Circuit for a Nonvolatile Memory Array
Method for Storing and Reading Data in a Multilevel Nonvolatile Memory
Interlaced Memory Device with Random or Sequential Access
Method for Storing Data in a Nonvolatile Memory
Reading Circuit and Method for a Multilevel Non-Volatile Memory
Method for Programming Nonvolatile Memory Cells with Program and Verify Algorithm Using a Staircase Voltage with Varying Step Amplitude
Method and Circuit for Generating Reference Voltages for Reading a Multilevel Memory Cell
Method for Erasing an Electrically Erasable Nonvolatile Memory Device, in Particular an Eeprom-Flash Memory Device, and an Electrically Erasable Nonvolatile Memory Device, in Particular an Eeprom-Flash Memory Device
Process for Manufacturing Electronic Devices Comprising Nonvolatile Memory Cells of Reduced Dimensions
Method for Storing and Reading Data in a Multilevel Nonvolatile Memory, and Architecture Therefor
Nonvolatile Storage Device and Self-Redundancy Method for the Same
Ion-Implantation Machine, Control Method Thereof, and Process for Manufacturing Integrated Devices
Integrated Resistive Elements with Silicidation Protection
Method and Device for Timing Random Reading of a Memory Device
Self-Aligned Integrated Electronic Devices
Method of Manufacturing Semiconductor Device
Method for Forming Bit Line of Flash Device
Method for Manufacturing Flash Memory Device
High Voltage Transfer Circuit
Method of Manufacturing Dual Gate Oxide Film
Method of Manufacturing Semiconductor Device
Method for Reading Flash Memory Cell, Nand-Type Flash Memory Apparatus, and nor-Type Flash Memory Apparatus
Method of Forming Gate Electrode in Flash Memory Device
Patent:
6,803,277 →
Application:
10/744,495 →
Mos Device and Process for Manufacturing Mos Devices Using Dual-Polysilicon Layer Technology
Mos Device and a Process for Manufacturing Mos Devices Using a Dual-Polysilicon Layer Technology with Side Contact
Analysis of the Quality of Contacts and Vias in Multi-Metal Fabrication Processes of Semiconductor Devices, Method and Test Chip Architecture
Method for Manufacturing Flash Memory Device
High Voltage Transistor and Method of Manufacturing the Same
Method of Forming Metal Line in Semiconductor Device
Circuit of Redundancy Io Fuse in Semiconductor Device
High Voltage Switch Circuit
Method for Manufacturing Flash Memory Device
Method of Generating an Enable Signal of a Standard Memory Core and Relative Memory Device
Nonlithographic Method of Defining Geometries for Plasma and/or Ion Implantation Treatments on a Semiconductor Wafer
Circuit for Selecting/Deselecting a Bitline of a Non-Volatile Memory
Method and Circuit for Verifying and Eventually Substituting Defective Reference Cells of a Memory
Method for Managing Bad Memory Blocks in a Nonvolatile Memory Device, and Nonvolatile-Memory Device Implementing the Management Method
Application:
11/152,675 →
Publication:
US 2006/0018166
Read/Verify Circuit for Multilevel Memory Cells with Ramp Read Voltage, and Read/Verify Method Thereof
Reading Circuit and Method for a Nonvolatile Memory Device
Charge-Pump Device with Increased Current Output
Method and Circuit for Simultaneously Programming Memory Cells
Control of Voltages During Erase and Re-Program Operations of Memory Cells
Circuit for Generating an Internal Enabling Signal for an Output Buffer of a Memory
Ramp Generator and Relative Row Decoder for Flash Memory Device
Nonvolatile Memory Device with Multiple References and Corresponding Control Method
Process for Digging a Deep Trench in a Semiconductor Body and Semiconductor Body So Obtained
Synchronization of Operations in Distinct Memory Partitions
Reduction of the Time for Executing an Externally Commanded Transfer of Data in an Integrated Device
Memory Device with Fail Search and Redundancy
Related Assignments
(7)
Other recorded transfers of the patents in this record — the chain of ownership.
Security Interest
May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
Patent Security Agreement
Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
Corrective Assignment to Correct the Replace Erroneously Filed Patent #7358718 with the Correct Patent #7358178 Previously Recorded on Reel 038669 Frame 0001. Assignor(S) Hereby Confirms the Security Interest.
Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
Security Interest
Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
Release of Security Interest
Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
Release of Security Interest
Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
Release of Security Interest
Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →