Control of voltages during erase and re-program operations of memory cells
View Patent ↗A method for verifying an array cell of a memory device may include determining after each erase pulse or program pulse the threshold of a cell addressed through a selected array word-line and bit-line, by applying an identical voltage ramp to the selected array word-line and to the control gate of a reference cell, while biasing at a certain voltage deselected word-lines through distribution lines of the voltage generated by a charge pump generator. The method may further include temporarily decoupling the deselected word-lines from the distribution lines of the bias voltage for the duration of the voltage ramp.
1. A method for verifying an array cell of a memory device comprising:
determining after an erase pulse or a program pulse a threshold of an array cell addressed through a selected word-line and a selected bit-line by applying an identical voltage ramp to the selected word-line and to a control gate of a reference cell while biasing at a bias voltage deselected word-lines through distribution lines of a voltage generated by a charge pump generator; and
temporarily decoupling the deselected word-lines from the distribution lines of the bias voltage for the duration of the voltage ramp.
2. The method of claim 1 wherein determining follows a applying a soft program pulse for recovering the array cell from a depleted condition and the bias voltage of deselected word-lines is of a sign and value sufficient to ensure turn off of any cell still depleted and that is coupled to the selected bit-line.
3. The method of claim 1 wherein the temporary decoupling is made by placing in a high impedance state the distribution line of the bias voltage to respective drivers of the deselected word-lines.
4. The method of claim 1 wherein the temporary decoupling is made by commanding stopping of the charge pump generator and by isolating a voltage divider that provides an estimation of a voltage output by said charge pump generator for a regulation loop thereof.
5. The method of claim 1 wherein the memory device comprises a multi-level two-bits/cell FLASH-EPROM device.
6. A method for verifying an array cell of a memory device comprising:
determining after an erase pulse or program pulse a threshold of an array cell addressed through a selected word-line and a selected bit-line by applying a corresponding voltage ramp to the selected word-line and to a control gate of a reference cell while biasing deselected word-lines through distribution lines; and
temporarily decoupling the deselected word-lines from the distribution lines during the voltage ramp.
7. The method of claim 6 wherein determining follows a applying a soft program pulse for recovering the array cell from a depleted condition and a bias voltage of deselected word-lines is of a sign and value sufficient to ensure turn off of any cell still depleted and that is coupled to the selected bit-line.
8. The method of claim 6 wherein the temporary decoupling is made by placing in a high impedance state the distribution line to respective drivers of the deselected word-lines.
9. The method of claim 6 wherein the temporary decoupling is made by commanding stopping of a charge pump generator supplying a bias voltage to the distribution line of the deselected word-lines.
10. The method of claim 9 wherein the temporary decoupling further comprises isolating a voltage divider that provides an estimation of a voltage output by the charge pump generator for a regulation loop thereof.
11. The method of claim 6 wherein the memory device comprises a multi-level two-bits/cell FLASH-EPROM device.
12. A memory device comprising:
an array of cells;
word-lines and bit-lines coupled to said cells;
distribution lines coupled to said word-lines;
a reference cell having a control gate; and
a control circuit for verifying a cell by determining after an erase pulse or program pulse a threshold of the cell addressed through a selected word-line and a selected bit-line by applying a corresponding voltage ramp to the selected word-line and to the control gate of the reference cell while biasing deselected word-lines through distribution lines, and temporarily decoupling the deselected array word-lines from the distribution lines during the voltage ramp.
13. The memory device of claim 12 wherein said control circuit applies a soft program pulse for recovering the cell from a depleted condition and a bias voltage of deselected array word-lines is of a sign and value sufficient to ensure turn off of any cell still depleted and that is coupled to the selected bit-line.
14. The memory device of claim 12 further comprising respective drivers for the word-lines; and wherein said control circuit makes the temporary decoupling by placing in a high impedance state the distribution line to respective drivers of the deselected word-lines.
15. The memory device of claim 12 further comprising a charge pump generator for supplying a bias voltage to the distribution line of the deselected word-lines; and wherein said control circuit makes the temporary decoupling by commanding stopping of said charge pump generator supplying the bias voltage to the distribution line of the deselected word-lines.
16. The memory device of claim 15 wherein said charge pump generator further comprises a voltage divider providing an estimation of a voltage output by said charge pump generator as part of a regulation loop; and wherein said control circuit further makes the temporary decoupling by isolating said voltage divider.
17. The memory device of claim 12 wherein said cells comprise multi-level two-bits/cells of a FLASH-EPROM type.