Circuit for generating an internal enabling signal for an output buffer of a memory
View Patent ↗A circuit is for generating an internal enabling signal for the output buffer of a memory as a function of external commands for enabling the memory and for outputting data. The circuit may be input with the external command for enabling the memory and with internally generated flags signaling when the memory is being read and when a read operation of data from the memory ends. The circuit may generate a first intermediate signal having a null logic value when the memory is enabled and the read operation of data from the memory ends. The circuit may further generate the internal enabling signal as a logic NOR between the first intermediate signal and a logic OR between the external command enabling the memory and the external command for outputting data.
1. A memory comprising:
an output buffer; and
a logic circuit configured to
receive one or more external commands to enable the memory and output data;
receive one or more internally generated flags to signal when the memory is being read and when a read operation of data from the memory ends;
generate a first intermediate signal with a null logic value when the memory is enabled and the read operation of data from the memory ends; and
generate an internal enabling signal for said output buffer as a function of a logic NOR between the first intermediate signal and a logic OR between the external command to enable the memory and the external command to output data.
2. The memory according to claim 1 , wherein said logic circuit comprises a logic NOR gate configured to
receive an inverted replica of of an external command, of the one or more external commands, to enable the memory, and the one or more internally generated flags to signal when the memory is being read and when the read operation ends; and
to generate a second intermediate signal.
3. The memory according to claim 2 , wherein said logic NOR gate is configured to receive a signal to enable a test function of the memory.
4. The memory according to claim 2 , wherein said logic circuit further comprises a latch configured to generate the first intermediate signal by being configured to sample the second intermediate signal based upon a sampling pulse signal.
5. The memory according to claim 4 , wherein said logic circuit further comprises a logic OR gate configured to
receive an external command, of the one or more external commands, to enable the memory, the one or more internally generated flags to signal when the memory is being read and when a read operation ends; and
to generate the sampling pulse signal.
6. The memory according to claim 1 , wherein said logic circuit comprises a logic OR gate configured to
receive an inverted replica of an external command, of the one or more external commands, to enable the memory, the one or more internally generated flags to signal when the memory is being read and when the read operation ends; and
generate a second intermediate signal.
7. The memory according to claim 6 , wherein said logic OR gate is configured to receive a signal to enable a test function of the memory.
8. The memory according to claim 6 , wherein said logic circuit further comprises a logic OR gate configured to
receive the external command to enable the memory, the one or more internally generated flags to signal when the memory is being read and when the read operation ends, and
generate an auxiliary signal.
9. The memory according to claim 8 , wherein said logic circuit further comprises
a latch to generate the first intermediate signal with a high logic value if the second intermediate signal is null, or with a null logic value if the second intermediate signal is high and the auxiliary signal is high; and wherein said latch is configured to leave unchanged the first intermediate signal when the second intermediate signal is high and the auxiliary signal is null.
10. A memory comprising:
an output buffer; and
a logic circuit configured to
receive one or more external commands to enable the memory and output data;
receive one or more internally generated flags to signal when the memory is being read and when a read operation of data from the memory ends;
generated a first intermediate signal with a first logic value when the memory is enabled and the read operation of data from the memory ends; and
generate an internal enabling signal for said output buffer as a function of
a logic function between the first intermediate signal and a result of a logic function between the external command to enable the memory and the external command to output data.
11. The memory according to claim 10 , wherein said logic circuit comprises a logic NOR gate configured to
receive an inverted replica of an external command, of the one or more external commands, to enable the memory, and the one or more internally generated flags to signal when the memory is being read and when the read operation ends; and
generate a second intermediate signal.
12. The memory according to claim 11 , wherein said logic NOR gate is configured to receive a signal to enable a test function of the memory.
13. The memory according to claim 11 , wherein said logic circuit further comprises a latch configured to generate the first intermediate signal by being configured to sample the second intermediate signal based upon a sampling pulse signal.
14. The memory according to claim 13 , wherein said logic circuit further comprises a logic OR gate configured to
receive the external command to enable the memory, and the one or more internally generated flags to signal when the memory is being read and when a read operation ends; and
generate the sampling pulse signal.
15. The memory according to claim 10 , wherein said logic circuit comprises a logic OR gate configured to
receive an inverted replica of an external command, of the one or more external commands, to enable the memory, and the one or more internally generated flags to signal when the memory is being read and when the read operation ends; and
generate a second intermediate signal.
16. The memory according to claim 15 , wherein said logic OR gate is configured to receive a signal to enable a test function of the memory.
17. The memory according to claim 15 , wherein said logic circuit further comprises a logic OR gate configured
receive the external command to enable the memory, and the one or more internally generated flags to signal when the memory is being read and when the read operation ends; and
generate an auxiliary signal.
18. The memory according to claim 17 , wherein said logic circuit further comprises a latch configured to generate the first intermediate signal with a high logic value if the second intermediate signal is null, or with a null logic value if the second intermediate signal is high and the auxiliary signal is high; and wherein said latch is further configured to leave unchanged the first intermediate signal when the second intermediate signal is high and the auxiliary signal is null.
19. A method for generating an internal enabling signal for the output buffer of a memory as a function of external commands for enabling the memory and for outputting data comprising:
inputting a logic circuit with the external command for enabling the memory and with internally generated flags signaling when the memory is being read and when a read operation of data from the memory ends;
using the logic circuit to generate a first intermediate signal having a first logic value when the memory is enabled and the read operation of data from the memory ends; and
using the logic circuit to generate the internal enabling signal as a logic function between the first intermediate signal and a result of a logic function between the external command enabling the memory and the external command for outputting data.
20. The method according to claim 19 , wherein the logic circuit comprises a logic NOR gate input with an inverted replica of the external command for enabling the memory signal, and input with the flags signaling when the memory is being read and when the read operation ends, and generating a second intermediate signal.
21. The method according to claim 20 , wherein the logic NOR gate is input with a signal for enabling a test function of the memory.
22. The method according to claim 20 , wherein the logic circuit further comprises a latch generating the first intermediate signal by sampling the second intermediate signal based upon a sampling pulse signal.
23. The method according to claim 22 , wherein the logic circuit further comprises a logic OR gate input with the external command for enabling the memory, the flags signaling when the memory is being read and when a read operation ends, and generating the sampling pulse signal.
24. The method according to claim 19 , wherein the logic circuit comprises a logic OR gate input with an inverted replica of the external command for enabling the memory, the flags signaling when the memory is being read and when the read operation and, and generating a second intermediate signal.
25. The method according to claim 24 , wherein the logic OR gate is input with a signal for enabling a test function of the memory.
26. The method according to claim 24 , wherein the logic circuit further comprises a logic OR gate input with the external command for enabling the memory, the flags signaling when the memory is being read and when the read operation ends, and generating an auxiliary signal.
27. The method according to claim 26 , wherein the logic circuit further comprises a latch generating the first intermediate signal having a high logic value if the second intermediate signal is null, or having a null logic value if the second intermediate signal is high and the auxiliary signal is high; and wherein the latch leaves unchanged the first intermediate signal when the second intermediate signal is high and the auxiliary signal is null.