Method for manufacturing flash memory device
View Patent ↗The present invention relates to a method for manufacturing a flash memory device. A plurality of conductive layers and dielectric layers are etched in a single etch apparatus, thus forming a control gate and a floating gate. In a gate formation process in which a thickness of a floating gate is over 1500 Å, problems in short process time and short mass production margin in an existing process can be solved while completely stripping a dielectric layer fence.
1. A method for manufacturing a flash memory device, comprising:
forming a tunnel oxide layer and a first conductive layer on a semiconductor substrate and then performing a shallow trench isolation process to form an isolation structure that defines a first region and a second region;
forming a second conductive layer on the entire structure and then patterning the second conductive layer and the first conductive layer to form a floating gate pattern;
forming a dielectric layer, a third conductive layer, a fourth conductive layer and a hard mask layer on the entire structure and then patterning the hard mask layer; and
forming a control gate and a floating gate by performing an etching process from the fourth conductive layer to the first conductive layer in a single etch apparatus using the hard mask layer as a mask;
wherein the etching process comprises the steps of:
(a) over-etching the fourth conductive layer;
(b) etching the third conductive layer to expose the dielectric layer on the first region, and performing over-etch for a thickness of the third conductive layer to expose the dielectric layer on the second region;
(c) etching the dielectric layer to expose a portion of the second conductive layer on the first region, and etching portions of the third conductive layer and the second conductive layer while stripping a portion of the dielectric layer on the second region;
(d) stripping the third conductive layer remaining on the second region;
(e) etching the second conductive layer on the first region and at the same time stripping the dielectric layer and the second conductive layer remaining on the second region; and
(f) stripping the first conductive layer.
2. The method as claimed in claim 1 , wherein the hard mask layer has a stack structure of an insulating layer and an anti-reflection layer.
3. The method as claimed in claim 2 , wherein the hard mask layer has one of a stack structure of an anti-reflection layer, a PE-TEOS layer and an anti-reflection layer, a stack structure of an anti-reflection layer, a plasma enhanced nitride layer and an anti-reflection layer, a stack structure of a PE-TEOS layer and an anti-reflection layer, and a stack structure of a nitride layer and an anti-reflection layer.
4. The method as claimed in claim 1 , wherein the hard mask layer is patterned by means of an etch process using a mixed gas of CF 4 /CHF 3 /O 2 or CF 4 /CHF 3 at a pressure of 80 to 150 mT.
5. The method as claimed in claim 4 , wherein in case of CF 4 and CHF 3 , CF 4 of 60 to 90 sccm and CHF 3 of 20 to 50 sccm are introduced so that CF 4 and CHF 3 are mixed in the ratio of 1.5:1 to 3:1.
6. The method as claimed in claim 4 , wherein in case of CF 4 and CHF 3 , CF 4 of 20 to 50 sccm and CHF 3 of 60 to 90 sccm are introduced so that CF 4 and CHF 3 are mixed in the ratio of 1:1.5 to 1:3.
7. The method as claimed in claim 3 , further comprising the step of performing an anneal process under nitrogen atmosphere after the anti-reflection layer is formed.
8. The method as claimed in claim 1 , wherein step (a) is implemented using a mixed gas of Cl 2 /CF 4 /N 2 or Cl 2 /SF 6 /N 2 at a pressure of 4 to 10 mT.
9. The method as claimed in claim 8 , wherein Cl 2 of 100 to 140 sccm and CF 4 of 10 to 20 sccm are introduced so that Cl 2 and CF 4 are mixed in the ratio of 6:1 to 8:1, and N 2 of 5 to 20 sccm is introduced.
10. The method as claimed in claim 8 , wherein Cl 2 of 100 to 140 sccm and SF 6 of 5 to 10 sccm are introduced so that Cl 2 and SF 4 are mixed in the ratio of 14:1 to 16:1, and N 2 of 5 to 20 sccm is introduced.
11. The method as claimed in claim 1 , wherein step (b) is implemented using a mixed gas of HBr and O 2 at a pressure of 30 to 70 mT.
12. The method as claimed in claim 11 , wherein HBr of 100 to 200 sccm and O 2 of 1 to 5 sccm are introduced so that HBr and O 2 are mixed in the ratio of 35:1 to 40:1.
13. The method as claimed in claim 1 , wherein step (c) is implemented by introducing CF 4 of 50 to 150 sccm at a pressure of 3 to 6 mT and applying the bias power of 50 to 150 W and the source power of 300 to 400 W.
14. The method as claimed in claim 1 , wherein step (d) is implemented by using a mixed gas of HBr/O 2 /He at a pressure of 20 to 50 mT and applying the bias power of 100 to 200 W.
15. The method as claimed in claim 14 , wherein HBr of 100 to 200 sccm, O 2 of 1 to 5 sccm and He of 50 to 100 sccm are introduced so that HBr/O 2 /He are mixed in the ratio of 70:1:30 to 80:1:40.
16. The method as claimed in claim 1 , wherein step (e) is implemented by introducing CF 4 of 10 to 200 sccm at a pressure of 4 to 10 mT and applying the bias power of 50 to 200 W and the source power of 300 to 700 W.
17. The method as claimed in claim 1 , wherein step (f) is implemented by introducing HBr of 150 to 200 sccm and He of 50 to 150 sccm and applying the bias power of 150 to 300 W and the source power of 300 to 600 W.