Ramp generator and relative row decoder for flash memory device
View Patent ↗A non-volatile memory device includes an array of memory cells organized into a plurality of array sectors, with each array sector being singularly addressable through an array wordline. An array of reference cells is addressable through a reference wordline. A respective voltage ramp generator is provided for each array sector for generating a voltage ramp on an array wordline for reading a memory cell therein, and is provided for each array of reference cells for generating a voltage ramp on a reference wordline for a reference cell therein. A respective row decoding circuit is coupled between each respective voltage ramp generator and corresponding reference wordline or array wordline. A current generator generates a current to be injected on a circuit node in a selected array sector and on a circuit node of the array of reference cells to produce on the circuit nodes a voltage ramp similar to the generated voltage ramp. A respective local ramp generating circuit is provided for each array sector and for the array of reference cells, and delivering a charge current based upon a capacitance of the circuit nodes of the corresponding addressed array wordline or reference wordline, towards the respective row decoder of the wordline.
1. A non-volatile memory device comprising:
an array of memory cells organized into a plurality of array sectors, each array sector singularly addressable through an array wordline;
at least one array of reference cells addressable through a reference wordline;
a respective voltage ramp generator for each array sector for generating a voltage ramp on an array wordline for reading a memory cell therein, and for each array of reference cells for generating a voltage ramp on a reference wordline for a reference cell therein;
a respective row decoding circuit coupled between each respective voltage ramp generator and corresponding reference wordline or array wordline; and
a current generator for generating a current to be injected on a circuit node in a selected array sector and on a circuit node of said at least one array of reference cells to produce on the circuit nodes a voltage ramp similar to the generated voltage ramp; and
a respective local ramp generating circuit for each array sector and for said at least one array of reference cells, and comprising a switch controlled by a ramp starting signal for delivering a charge current based upon a capacitance of the circuit nodes of the corresponding addressed array wordline or reference wordline, towards the respective row decoder of the wordline.
2. A nonvolatile memory device according to claim 1 , wherein each local ramp generating circuit comprises a current mirror having an output node connected to an input node of a respective row decoding circuit and to said switch; and wherein said switch keeps said local ramp generating circuit at a common ground potential of the memory until a pulse having a preestablished duration for starting a voltage ramp is received.
3. A nonvolatile memory device according to claim 1 , wherein each local ramp generating circuit comprises a current mirror, and a selection switch connected to said current mirror, each selection switch being connected to a distribution line; and wherein said current generator is configured as a high precision current generator that supplies the current through said distribution line to each local ramp generating circuit via said corresponding selection switch.
4. A non-volatile memory device according to claim 3 , wherein said high precision current generator comprises a matched pair of output transistors coupled to another transistor for forming a current mirror, and wherein the current generated by said high precision current generator is provided through said matched pair of output transistors of said current mirror, with dimensions of said matched pair of output transistors being trimmed for delivering identical currents to the array wordline and reference wordline.
5. A non-volatile memory device according to claim 4 , wherein each row decoder provides for a charge current path for the capacitance of the selected array wordline that includes a single MOS transistor.
6. A non-volatile memory device according to claim 3 , further comprising an auxiliary precharge current generator for pre-charging the capacitances of the circuit nodes coinciding with said distribution lines of the current precisely established on said local ramp generators of the selected array sector and towards the array of reference cells up to a voltage close to but less than a pre-established value for starting the voltage ramp.
7. A memory device comprising:
an array of memory cells organized into a plurality of array sectors, each array sector singularly addressable through an array wordline;
at least one array of reference cells addressable through a reference wordline;
a respective voltage ramp generator for each array sector for generating a voltage ramp on an array wordline for reading a memory cell therein, and for each array of reference cells for generating a voltage ramp on a reference wordline for a reference cell therein;
a respective row decoding circuit coupled between each respective voltage ramp generator and corresponding reference wordline or array wordline;
a current generator for generating a current to be injected on a circuit node in a selected array sector and on a circuit node of said at least one array of reference cells to produce on the circuit nodes a voltage ramp similar to the generated voltage ramp; and
a respective local ramp generating circuit for each array sector and for said at least one array of reference cells, and delivering a charge current based upon a capacitance of the circuit nodes of the corresponding addressed array wordline or reference wordline, towards the respective row decoder of the wordline.
8. A non-volatile memory device according to claim 7 , wherein each respective local ramp generating circuit comprises a switch controlled by a ramp starting signal for delivering the charge current.
9. A nonvolatile memory device according to claim 8 , wherein each local ramp generating circuit comprises a current mirror having an output node connected to an input node of a respective row decoding circuit and to said switch; and wherein said switch keeps said local ramp generating circuit at a common ground potential of the memory until a pulse having a preestablished duration for starting a voltage ramp is received.
10. A non-volatile memory device according to claim 9 , wherein each local ramp generating circuit comprises a current mirror, and a selection switch connected to said current mirror, each selection switch being connected to a distribution line; and wherein said current generator is configured as a high precision current generator that supplies the current through said distribution line to each local ramp generating circuit via said corresponding selection switch.
11. A non-volatile memory device according to claim 10 , wherein said high precision current generator comprises a matched pair of output transistors coupled to another transistor for forming a current mirror, and wherein the current generated by said high precision current generator is provided through said matched pair of output transistors of said current mirror, with dimensions of said matched pair of output transistors being trimmed for delivering identical currents to the array wordline and reference wordline.
12. A non-volatile memory device according to claim 7 , wherein each row decoder provides for a charge current path for the capacitance of the selected array wordline that includes a single MOS transistor.
13. A nonvolatile memory device according to claim 9 , further comprising an auxiliary precharge current generator for pre-charging the capacitances of the circuit nodes coinciding with said distribution lines of the current precisely established on said local ramp generators of the selected array sector and towards the array of reference cells up to a voltage close to but less than a pre-established value for starting the voltage ramp.
14. A method for reading a non-volatile memory device comprising an array of memory cells organized into a plurality of array sectors, each array sector singularly addressable through an array wordline; and at least one array of reference cells addressable through a reference wordline, the method comprising:
using a respective voltage ramp generator for each array sector for generating a voltage ramp on an array wordline for reading a memory cell therein, and for each array of reference cells for generating a voltage ramp on a reference wordline for a reference cell therein;
using a respective row decoding circuit coupled between each respective voltage ramp generator and corresponding reference wordline or array wordline for selecting a memory cell and corresponding reference cell;
generating a current to be injected on a circuit node in a selected array sector and on a circuit node of the at least one array of reference cells to produce on the circuit nodes a voltage ramp similar to the generated voltage ramp; and
using a respective local ramp generating circuit for each array sector and for the at least one array of reference cells, and delivering a charge current based upon a capacitance of the circuit nodes of the corresponding addressed array wordline or reference wordline, towards the respective row decoder of the wordline.
15. A method according to claim 14 , wherein each respective local ramp generating circuit comprises a switch controlled by a ramp starting signal for delivering the charge current.
16. A method according to claim 15 , wherein each local ramp generating circuit comprises a current mirror having an output node connected to an input node of a respective row decoding circuit and to the switch; and wherein the switch keeps the local ramp generating circuit at a common ground potential of the memory until a pulse having a pre-established duration for starting a voltage ramp is received.
17. A method according to claim 16 , wherein each local ramp generating circuit comprises a current mirror, and a selection switch connected to the current, each selection switch being connected to a distribution line; and wherein the current generator is configured as a high precision current generator that supplies the current through the distribution line to each local ramp generating circuit via the corresponding selection switch.
18. A method according to claim 17 , wherein the high precision current generator comprises a matched pair of output transistors coupled to another transistor for forming a current mirror, and wherein the current generated by the high precision current generator is provided through the matched pair of output transistors of the current mirror, with dimensions of the matched pair of output transistors being trimmed for delivering identical currents to the array wordline and reference wordline.
19. A method according to claim 14 , wherein each row decoder provides for a charge current path for the capacitance of the selected array wordline that includes a single MOS transistor.
20. A method according to claim 17 , further comprising an auxiliary precharge current generator for pre-charging the capacitances of the circuit nodes coinciding with the distribution lines of the current precisely established on the local ramp generators of the selected array sector and towards the array of reference cells up to a voltage close to but less than a preestablished value for starting the voltage ramp.