Reduction of the time for executing an externally commanded transfer of data in an integrated device
View Patent ↗Cumulative delay contributions introduced by an input buffer and by the metal line that distributes the buffered external control signal to data transfer circuits for performing a transfer of data to and from an integrated device are reduced by having the external signal distributed unbuffered through a metal line of sufficiently large size. This introduces a negligible intrinsic propagation delay being within the specified maximum admitted input pad capacitance. The delay reduction is also based on locally dedicated input buffers for each data transfer circuit, and for applying thereto a buffered replica of the external signal present on the metal line.
1. A method comprising:
receiving, by an integrated circuit, a control signal from an external device;
distributing the control signal unbuffered through a distributing line of the integrated circuit to a first decoupling input buffer and a second decoupling input buffer;
producing, with the first decoupling input buffer, a first buffered replica of the control signal;
transmitting, with the first decoupling input buffer, the first buffered replica solely to a flip flop or an enabling node of an address buffer of a first data transfer circuit;
producing, with the second decoupling input buffer, a second buffered replica of the control signal; and
transmitting, with the second decoupling input buffer, the second buffered replica solely to a flip flop or an enabling node of an address buffer of a second data transfer circuit.
2. The method of claim 1 , wherein the integrated circuit comprises an input pad having an allowed input pad capacitance and coupled to the distributing line, the distributing line having a width corresponding to the allowed input pad capacitance.
3. The method of claim 1 , wherein the control signal comprises a synchronizing signal or an enabling signal.
4. The method of claim 1 , wherein said transmitting the first buffered replica comprises transmitting the first buffered replica solely to the flip flop of the first data transfer circuit, said transmitting the second buffered replica comprises transmitting the second buffered replica solely to the flip flop of the second data transfer circuit, and the method further comprises:
receiving, by the integrated circuit, another control signal from the external device,
distributing the another control signal unbuffered through another distributing line of the integrated circuit;
producing, with a third decoupling input buffer, a third buffered replica of the another control signal;
transmitting, with the third decoupling input buffer, the third buffered replica solely to the enabling node of the address buffer of the first data transfer circuit;
producing, with a fourth decoupling input buffer, a fourth buffered replica of the another control signal; and
transmitting, with the fourth decoupling input buffer, the fourth buffered replica solely to the enabling node of the address buffer of the second data transfer circuit.
5. The method of claim 4 , wherein the integrated circuit comprises a nonvolatile flash memory device, the control signal is a clock signal, and the another control signal is an enabling signal.
6. A structure comprising:
a distributing line coupled to an input pad of an integrated device to receive an externally generated signal and to provide an unbuffered distribution of the externally generated signal; and
a first decoupling input buffer and a second decoupling input buffer coupled to the distributing line to receive the unbuffered distribution of the externally generated signal, the first decoupling input buffer configured to produce a first buffered replica of the externally generated signal and to transmit the first buffered replica solely to a flip flop or an enabling node of an address buffer of a first data transfer circuit, and the second decoupling input buffer configured to produce a second buffered replica of the externally generated signal and to transmit the second buffered replica solely to a flip flop or an enabling node of an address buffer of a second data transfer circuit.
7. The structure of claim 6 , wherein the externally generated signal comprises a synchronizing signal or an enabling signal.
8. The structure of claim 6 , wherein the first decoupling input buffer is configured to transmit the first buffered replica solely to the flip flop of the first data transfer circuit, the second decoupling input buffer is configured to transmit the second buffered replica solely to the flip flop of the second data transfer circuit and the structure further comprises:
another distributing line coupled to another input pad of the integrated device to receive another externally generated signal and to provide an unbuffered distribution of the another externally generated signal; and
a third decoupling input buffer and a fourth decoupling input buffer coupled to the another distributing line to receive the unbuffered distribution of the another externally generated signal, the third decoupling input buffer configured to produce a third buffered replica of the another externally generated signal and to transmit the third buffered replica solely to the enabling node of the address buffer of the first data transfer circuit, and the fourth decoupling input buffer configured to produce a fourth buffered replica of the another externally generated signal and to transmit the fourth buffered replica solely to the enabling node of the address buffer of the second data transfer circuit.
9. The structure of claim 6 , wherein the integrated device comprises a nonvolatile flash memory device, the externally generated signal is a clock signal, and the another externally generated signal is an enabling signal.
10. The structure of claim 6 , wherein the input pad is associated with an allowed input pad capacitance, and said distributing line has a width corresponding to the allowed input pad capacitance.
11. An integrated device comprising:
an input pad to receive an externally generated signal;
a distributing line coupled to the input pad to provide an unbuffered distribution of the externally generated signal;
a first data transfer circuit having a flip flop and an address buffer;
a second data transfer circuit having a flip flop and an address buffer;
a first decoupling input buffer coupled to the distributing line and the first data transfer circuit and configured to receive the unbuffered distribution of the externally generated signal from the distributing line, to produce a first buffered replica of the externally generated signal, and to transmit the first buffered replica solely to the flip flop or an enabling node of the address buffer of the first data transfer circuit; and
a second decoupling input buffer coupled to the distributing line and the second data transfer circuit and configured to receive the unbuffered distribution of the externally generated signal from the distributing line, to produce a second buffered replica of the externally generated signal, and to transmit the second buffered replica solely to the flip flop or an enabling node of the address buffer of the second data transfer circuit.
12. The integrated device of claim 11 , wherein the externally generated signal comprises a synchronizing signal or an enabling signal.
13. The integrated device of claim 11 , wherein the first decoupling input buffer is configured to transmit the first buffered replica solely to the flip flop of the first data transfer circuit, the second decoupling input buffer is configured to transmit the second buffered replica solely to the flip flop of the second data transfer circuit and the integrated device further comprises:
another input pad;
another distributing line coupled to the another input pad to receive another externally generated signal and to provide an unbuffered distribution of the another externally generated signal;
a third decoupling input buffer coupled to the another distributing line and the first data transfer circuit and configured to receive the unbuffered distribution of the another externally generated signal from the another distributing line, to produce a third buffered replica of the another externally generated signal, and to transmit the third buffered replica solely to the enabling node of the address buffer of the first data transfer circuit; and
a fourth decoupling input buffer coupled to the another distributing line and the second data transfer circuit and configured to receive the unbuffered distribution of the another externally generated signal from the another distributing line, to produce a fourth buffered replica of the another externally generated signal, and to transmit the fourth buffered replica solely to the enabling node of the address buffer of the second data transfer circuit.
14. The integrated device of claim 13 , wherein the externally generated signal is a clock signal and the another externally generated signal is an enabling signal.
15. The integrated device of claim 11 , wherein the input pad is associated with an allowed input pad capacitance, and said distributing line has a width corresponding to the allowed input pad capacitance.