Method of manufacturing semiconductor device
View Patent ↗A method of manufacturing a semiconductor device is disclosed which comprises, forming a first well region by performing an ion implantation process for implanting first ions into a semiconductor substrate, and then forming a second well region in the first well region by performing an ion implantation process for implanting second ions having larger mass than the first ions; and forming a three-part or three-fold well region by performing an annealing process on the result structure wherein the lighter first ions are disposed in the upper and lower well regions and the heavier second ions are disposed in the middle well region. Therefore, it is possible to prevent TED phenomenon generated due to the high-energy heat treatment process to be performed later and to provide the increased activation ratio of ions compared to the conventional source/drain region in which only the ions having large mass are implanted by performing an annealing process after the first well region and the second well region are formed.
1. A method of manufacturing a semiconductor device, comprising:
performing a first ion implantation process for implanting first ions into a first region of a semiconductor substrate;
performing a second ion implantation process for implanting second ions into the first region wherein the second ions having a larger mass than the first ions; and
performing an annealing process on the resulting structure to form a three-fold well region having a first lower well region implanted with the first ions, a second middle well region implanted with the second ions and a third upper well region implanted with the first ions.
2. A method of claim 1 , wherein the first ion implantation process is performed by implanting phosphorus (P) ions at a tilt angle in the range of 3° to 13° with a dose in the range of 1E11 ions/cm 2 to 1E14 ions/cm 2 at an energy in the range of about 500 KeV to 3000 KeV, by using a high-energy ion implantation device.
3. A method of claim 1 , wherein the second ion implantation process is performed by implanting arsenic (As) ions having larger mass than phosphorus ions, at a tilt angle in the range of 3° to 13° with a dose in the range of 1E11 ions/cm 2 to 1E14 ions/cm 2 at an energy in the range of about 100 KeV to 300 KeV, by using a middle-current ion implantation device.
4. A method of claim 1 , wherein the annealing process is performed using one of an RTP process performed under N 2 or H 2 gas atmosphere at a temperature in the range of 900° C. to 1000° C. for a time period in the range of 10 minutes to 60 seconds, or a furnace process performed under N 2 or H 2 gas atmosphere at a temperature in the range of 900° C. to 1100° C. for a time period in the range of 10 minutes to 60 minutes.
5. A method of claim 1 , further comprising forming a region into which ions for adjusting a threshold voltage are implanted on the semiconductor substrate on which well regions are formed, and then forming a tunnel oxide film, a floating gate electrode, a dielectric film and a control gate electrode on an upper part of the semiconductor substrate.
6. A method of claim 1 , further comprising forming a screen oxide film serving as a buffer layer for suppressing a damage generated by the ion implantation process for forming the first well region and the second well region before forming the well region.