Granted Patent B2

US 7,072,216 · App. 10/740,100 · Granted Jul 4, 2006

Abstract

Claims (6)

1. A method for reading a flash memory cell having a gate terminal, a drain terminal, and a source terminal, comprising the steps of:

applying a channel voltage to the gate terminal, applying a read voltage to the drain terminal, and applying a power supply voltage to the source terminal, wherein the channel voltage is lower than a threshold voltage of the cell in a programmed state and higher than a threshold voltage of the cell in an erased state, wherein the read voltage is lower than the power supply voltage and higher than a ground voltage; and

reading information stored in the cell by comparing a voltage of the drain terminal with a reference voltage.

2. The method for reading a flash memory cell according to claim 1 , wherein the cell is read as the programmed state when the read voltage applied to the drain terminal is equal to or lower than the reference voltage, and the cell is read as the erased state when the read voltage applied to the drain terminal is higher than the reference voltage.

3. The method for reading a flash memory cell according to claim 1 , wherein the read voltage is used as the reference voltage.

4. The method for reading a flash memory cell according to claim 1 , wherein a voltage of 1 V or a half of the power supply voltage is used as the read voltage.

Assignments (10)