Analysis of the quality of contacts and vias in multi-metal fabrication processes of semiconductor devices, method and test chip architecture
View Patent ↗A test chip performs measurements to evaluate the performances of interconnects. In particular, the statistical failure distribution, the electromigration and the leakage current are measured. An algorithm detects a via failure at any of the available n metal layers. The test chip includes a ROM memory array. The vias to be measured are formed in the columns of the array. Via or contact failures are detected by forcing a predetermined current through both an array column and a reference column. The failure analysis is obtained by comparing the resulting voltage drops.
1. A method for analyzing a quality of contacts and vias using a test chip, the test chip comprising a substrate; a plurality of contacts on the substrate and defining a zero level; and a test array on the substrate comprising a plurality of conductive levels and a plurality of individually selectable vias separating the plurality of conductive levels, each conductive level comprising a plurality of nodes with each node being connected to at least one individually selectable via, the plurality of conductive levels and the plurality of individually selectable vias forming a pyramidal interconnect structure so that an electrical path between a contact at the zero level and a node on one of the plurality of conductive levels includes at least one individually selectable via therebetween, the method comprising:
selecting an electrical path in the pyramidal interconnect structure between a contact at the zero level and a node on one of the plurality of conductive levels; and
measuring an electrical resistance of the selected electrical path.
2. A method according to claim 1 , further comprising comparing the measured electrical resistance to a reference threshold.
3. A method according to claim 1 , wherein all possible electrical paths are selected and measured for obtaining a failure diagram for identifying locations of faulty contacts and vias.
4. A method according to claim 3 , wherein the plurality of conductive levels is equal to n, with n being ≧2, and there are F possible electrical path locations defined by
F
=
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i
=
1
n
2
i
.
5. A method according to claim 1 , wherein each contact is connected to a single individually selectable via; and wherein each node is connected to at least a pair of individually selectable vias.
6. A method according to claim 5 , wherein the plurality of conductive levels is equal to n, with n being ≧2, and any node on an nth conductive level is included in 2 n adjacent electrical paths.
7. A method according to claim 1 , wherein the test chip further comprises a plurality of word lines connected between a column address decoder and the test array, and a plurality of bit lines connected between a row address decoder and the test array; the test array comprising a plurality of AND connected transistors, each transistor comprising a control terminal connected a word line and a pair of conducting terminals connected to a respective bit line.
8. A method according to claim 7 , wherein the pair of conducting terminals for each transistor belong to a same column of the test array.
9. A method according to claim 7 , wherein the array of AND connected transistors are separated into even and odd transistors; and wherein the row decoder comprises an odd decoder for selecting the odd transistors and an even decoder for selecting the even transistors.
10. A test chip for analyzing, a quality of contacts and vias, the test chip comprising:
a substrate;
an active area in said substrate, said active area comprising a plurality of contacts and defining a zero level;
a test array on said substrate comprising a plurality of conductive levels and a plurality of individually selectable vias separating said plurality of conductive levels, each conductive level comprising a plurality of nodes with each node being connected to at least one individually selectable via, said plurality of conductive levels and said plurality of individually selectable vias forming a pyramidal interconnect structure so that an electrical path between a contact at the zero level and a node on one of said plurality of conductive levels includes at least one individually selectable via therebetween;
row and column address decoders connected to said test array for selecting an electrical path between a contact at the zero level and a node on one of said plurality of conductive levels; and
a sensing circuit for measuring an electrical resistance of the selected electrical path.
11. A test chip according to claim 10 , wherein each contact is connected to a single individually selectable via; and wherein each node is connected to at least a pair of individually selectable vias.
12. A test chip according to claim 11 , wherein said plurality of conductive levels is equal to n, with n being ≧2, and any node on an nth conductive level is included in 2 n adjacent electrical paths.
13. A test chip according to claim 10 , further comprising a plurality of word lines connected between said column address decoder and said test array, and a plurality of bit lines connected between said row address decoder and said test array; said test array comprising a plurality of AND connected transistors, each transistor comprising a control terminal connected a word line and a pair of conducting terminals connected to a respective bit line.
14. A test chip according to claim 13 , wherein the pair of conducting terminals for each transistor belong to a same column of said test array.
15. A test chip according to claim 13 , wherein said plurality of AND connected transistors are separated into even and odd transistors; and wherein said row decoder comprises an odd decoder for selecting said odd transistors and an even decoder for selecting said even transistors.
16. A test chip for analyzing a quality of contacts and vias, the test chip comprising;
a substrate;
an active area in said substrate, said active area comprising a plurality of contacts and defining a zero level;
a test array on said substrate comprising a plurality of conductive levels and a plurality of individually selectable vias separating said plurality of conductive levels, each conductive level comprising a plurality of nodes with each node being connected to at least one individually selectable via, said plurality of conductive levels and said plurality of individually selectable vias forming a pyramidal interconnect structure so that an electrical path between a contact at the zero level and a node on one of said plurality of conductive levels includes at least one individually selectable via therebetween;
a plurality of word lines connected to said test array, and a plurality of bit lines connected to said test array;
row and column address decoders respectively connected to said plurality of word lines and bit lines for selecting an electrical path between a contact at the zero level and a node on one of said plurality of conductive levels; and
a sensing circuit for measuring an electrical resistance of the selected electrical path.
17. A test chip according to claim 16 , wherein each contact is connected to a single individually selectable via; and wherein each node is connected to at least a pair of individually selectable vias.
18. A test chip according to claim 17 , wherein said plurality of conductive levels is equal to n, with n being ≧2, and any node on an nth conductive level is included in 2 n adjacent electrical paths.
19. A test chip according to claim 16 , wherein said test array comprises a plurality of AND connected transistors, each transistor comprising a control terminal connected a respective word line and a pair of conducting terminals connected to a respective bit line.
20. A test chip according to claim 19 , wherein the pair of conducting terminals for each transistor belong to a same column of said test array.
21. A test chip according to claim 19 , wherein said plurality of AND connected transistors are separated into even and odd transistors; and wherein said row decoder comprises an odd decoder for selecting said odd transistors and an even decoder for selecting said even transistors.