High voltage switch circuit
View Patent ↗The present invention discloses a high voltage switch circuit of a semiconductor device which can reduce a discharge time by supplying a higher voltage than a power voltage to a gate terminal of a discharge transistor in a discharge unit for discharging a high voltage.
1. A high voltage switch circuit, comprising:
a discharge node;
a high voltage switch unit for switching an external high voltage according to a high voltage transmission enable signal and a clock signal;
a first NMOS transistor for discharging a high voltage which is the output from the high voltage switch unit according to the discharge node;
a power voltage transmission unit for transmitting a power voltage to the discharge node according to the high voltage transmission enable signal;
a second NMOS transistor for controlling a voltage of the discharge node according to the high voltage transmission enable signal; and
a voltage pumping unit for increasing the voltage of the discharge node by a predetermined level according to the high voltage transmission enable signal and the clock signal.
2. The circuit of claim 1 , wherein the power voltage transmission unit includes a PMOS transistor and a third NMOS transistor connected in series between the power voltage and the discharge node.
3. The circuit of claim 2 , wherein the PMOS transistor is driven according to the high voltage transmission enable signal, and the third NMOS transistor is driven according to the power voltage transmitted through the PMOS transistor.
4. The circuit of claim 1 , wherein the voltage pumping unit includes:
an inverter for inverting the high voltage transmission enable signal;
a NAND gate for NANDing the output from the inverter and the clock signal; and
a fourth NMOS transistor capacitor-coupled for increasing the voltage of the discharge node by the predetermined level according to the output from the NAND gate.
5. A high voltage switch circuit, comprising:
a discharge node;
a high voltage switch unit for switching an external high voltage according to a high voltage transmission enable signal and a clock signal;
a first NMOS transistor for discharging a high voltage which is the output from the high voltage switch unit according to the discharge node;
a power voltage transmission unit for transmitting a power voltage to the discharge node according to the high voltage transmission enable signal, wherein the power voltage transmission unit includes a PMOS transistor and a third NMOS transistor connected in series between the power voltage and the discharge node;
a second NMOS transistor for controlling a voltage of the discharge node according to the high voltage transmission enable signal; and
a voltage pumping unit for increasing the voltage of the discharge node by a predetermined level according to the high voltage transmission enable signal and the clock signal, wherein the voltage pumping unit includes an inverter for inverting the high voltage transmission enable signal, a NAND gate for NANDing the output from the inverter and the clock signal and a fourth NMOS transistor capacitor-coupled for increasing the voltage of the discharge node by the predetermined level according to the output from the NAND gate.
6. The circuit of claim 5 , wherein the PMOS transistor is driven according to the high voltage transmission enable signal, and the third NMOS transistor is driven according to the power voltage transmitted through the PMOS transistor.