IP Library › Granted Patent US 7,169,695
Granted Patent B2
US 7,169,695 · App. 10/674,675 · Granted Jan 30, 2007

Method for forming a dual damascene structure

Assignee: Lam Research Corporation
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,169,695
App. No.
10/674,675
Granted
Jan 30, 2007
Kind
B2
Abstract

A method for forming a dual damascene feature is provided. Vias are formed in an etch layer. A trench patterned mask is provided over the etch layer. A trench is etched, where the etching the trench comprises a cycle of forming protective sidewalls over the sidewalls of the vias and etching a trench through the trench patterned mask. The mask is then stripped.

Claims (21)

1. A method for forming a dual damascene feature while preventing faceting and fence formation comprising:

forming vias in an etch layer;

providing a trench patterned mask over the etch layer;

etching a trench into the etch layer, wherein the etching the trench comprises a cycle of:

forming protective sidewalls over the sidewalls of the vias; and

etching a trench through the trench patterned mask; and

stripping the mask; and

repeating the trench cycle at least three times.

2. The method as recited in claim 1 , wherein the trench etch cycle is repeated at least five times.

3. The method, as recited in claim 2 , wherein the passivation and etching are performed in a common plasma processing chamber.

4. The method, as recited in claim 3 , wherein the deposition uses a non-directional deposition and the etching step uses a directional etching.

5. The method, as recited in claim 4 , wherein the wafer is bombarded by energetic ions with ionic energy greater than 100 ev during the deposition step.

6. The method, as recited in claim 4 , wherein the passivation is a non-etching or a negligibly etching deposition.

7. The method, as recited in claim 6 , wherein the deposition process is selected from at least one of chemical vapor deposition and sputtering.

8. The method, as recited in claim 4 , wherein the deposition step uses a mixture containing CF4 and H2.

9. The method as recited in claim 8 , wherein the CF4 to H2 gas flow ratio is in the range of 0.6:1 to 1.4:1 by volume flow rate.

10. The method, as recited in claim 4 , wherein the deposition uses a gas mixture containing at least one of H2, CH3F, CH2F2, CHF3, C4F6, C4F8 as the polymer former and at least one of CF4, C2F6, and NF3 as the etching gas.

11. The method, as recited in claim 10 , wherein the etching uses an etching gas mixture with components and wherein the forming the protective sidewalls uses a deposition gas mixture with components, wherein at least some of the components of the deposition gas mixture are not mixed with at least some of the components of the etching gas mixture.

12. The method, as recited in claim 1 , wherein the etch layer is a low-k dielectric material.

13. The method, as recited in claim 1 , wherein the via holes are not filled with a sacrificial filler material prior to the start of the trench plasma etching process.

14. The method, as recited in claim 1 , wherein the via holes are filled with a filler material to no more than 50% of the via hole height prior to the start of the trench plasma etching process.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 29, 2003
From: HUANG, ZHISONG; LI, LUMIN; SADJADI, REZA
To: LAM RESEARCH CORPORATION
Reel/Frame 014565/0665 →
Continuity (3)
Continuation In Part 1029560100 · Nov 14, 2002
Provisional Application 6041780600 · Oct 11, 2002
Related Publication 20040072430A1 · Apr 15, 2004