Semiconductor memory device using open data line arrangement
View Patent ↗When a phase shift method is used as lithography where sense amplifiers are alternately placed in a one intersecting-point memory capable of implementing a reduction in the area of a DRAM, it was difficult to layout data lines in a boundary region between sense amplifiers and each memory array. Therefore, there is provided a semiconductor device according to the present invention. In the semiconductor device, two data lines continuous within the sub memory arrays or interposed therebetween are connected to the adjacent sense amplifiers as a system for drawing data lines from sub memory arrays (SMA) to sense amplifiers (SA) when the sense amplifiers are alternately placed. Namely, the number of data lines interposed between data lines respectively connected to two adjacent sense amplifiers is set to even numbers (0, 2, 4, . . . ). Owing to the above configuration, a break and a short circuit in a portion where a sense amplifier block and a sub memory array are connected, can be avoided, and a connection layout is facilitated.
1. A semiconductor device, comprising:
a first memory block having a plurality of first memory cells coupled to a plurality of first data lines and a first word line;
a second memory block having a plurality of second memory cells coupled to a plurality of second data lines and a second word line; and
a first block provided between the first and second memory blocks and including a plurality of sense amplifiers,
wherein each of said plurality of sense amplifiers is coupled to one of said plurality of first data lines and one of said plurality of second data lines,
wherein each sense amplifier has a first P type MISFET, a second P type MISFET, a first N type MISFET, and a second N type MISFET,
wherein gates of said first P type MISFET and said first N type MISFET are electrically coupled together, and drains of said second P type MISFET and said second N type MISFET are electrically coupled together,
wherein gates of said second P type MISFET and said second N type MISFET are electrically coupled together, and drains of said first P type MISFET and said first N type MISFET are electrically coupled together, and
wherein a first semiconductor region forming said drain of first P type MISFET is more than half surrounded by a first layer forming said gate of said first P type MSFET.
2. The semiconductor device according to claim 1 ,
wherein said first layer and a second layer forming said gate of said first N type MISFET are different layers and are connected by a first metal layer formed above said first and second layers.
3. The semiconductor device according to claim 2 ,
wherein said first semiconductor region is a part of a first active region in a N type well, and
wherein a portion of said first layer surrounding said first semiconductor region is completely formed on top of said first active region.
4. The semiconductor device according to claim 3 ,
wherein said first and second memory cells are DRAM memory cells,
wherein second and third semiconductor regions each forming said drain and source of said second P type MISFET are a part of said first active region, and
wherein said second semiconductor region forming said drain of said second P type MISFET is more than half surrounded by a third layer forming said gate of said second P type MISFET.
5. The semiconductor device according to claim 4 ,
wherein said third layer and a fourth layer forming said gate of said second N type MISFET are different layers and are connected by a second metal layer formed above said third and fourth layers, and
said second metal layer is formed in the same metallization level as said first metal layer.
6. The semiconductor device according to claim 5 ,
wherein a fourth semiconductor region forming said drain of said first N type MISFET is more than half surrounded by said second layer, and
wherein a portion of said second layer surrounding said fourth semiconductor region is completely formed on top of a second active region in a P type substrate.
7. The semiconductor device according to claim 6 ,
wherein a fifth semiconductor region forming said drain of said second N type MISFET is more than half surrounded by said fourth layer, and
wherein a portion of said fourth layer surrounding said fifth semiconductor region is completely formed on top of said second active region.
8. The semiconductor device according to claim 6 ,
wherein said first metal layer is connected to said drain of said second P type MISFET through a contact hole and to said drain of said second N type MISFET through a contact hole.
9. The semiconductor device according to claim 8 ,
wherein said second metal layer is connected to said drain of said first P type MISFET through a contact hole and to said drain of said first N type MISFET through a contact hole.
10. A semiconductor device comprising:
a first memory block having a plurality of first DRAM memory cells coupled to a plurality of first data lines and a first word line;
a second memory block having a plurality of second DRAM memory cells coupled to a plurality of second data lines and a second word line; and
a first block provided between the first and second memory blocks and including a plurality of sense amplifiers,
wherein each of said plurality of sense amplifiers is coupled to one of said plurality of first data lines and one of said plurality of second data lines,
wherein each sense amplifier has a first P type MISFET, a second P type MISFET, a first N type MISFET, and a second N type MISFET,
wherein gates of said first P type MISFET and said first N type MISFET are electrically coupled together, and drains of said second P type MISFET and said second N type MISFET are electrically coupled together,
wherein gates of said second P type MISFET and said second N type MISFET are electrically coupled together, and drains of said first P type MISFET and said first N type MISFET are electrically coupled together,
wherein said gates of said first and second P type MISFETS and of said first and second N type MISFETs are made from separate layers in the same level, respectively,
wherein semiconductor regions each forming said drains of said first and second P type MISFETs are each surrounded on three sides of a rectangle by the gates of said first and second P type MISFETs, respectively, and
wherein semiconductor regions each forming said drains of said first and second N type MISFETs are each surrounded on three sides of a rectangle by the gates of said first and second N type MISFETs, respectively.
11. The semiconductor device according to claim 10 , further comprising:
a first metal layer connecting said layer forming said gate of said first P type MISFET and said layer forming said gate of said first N type MISFET, and connecting said drains of said second P type MISFET and said second N type MISFET through contact holes; and
a second metal layer connecting said layer forming said gate of said second P type MISFET and said layer forming said gate of said second N type MISFET, and connecting said drains of said first P type MISFET and said first N type MISFET through contact holes.
12. The semiconductor device according to claim 11 ,
wherein said plurality of first and second data lines are formed by lithography using phase shift masks.