IP Library Granted Patent US 7,292,622
Granted Patent B2
US 7,292,622 · App. 10/680,492 · Granted Nov 6, 2007

Method and apparatus for raking in a wireless network

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Quick Facts
Patent No.
US 7,292,622
App. No.
10/680,492
Granted
Nov 6, 2007
Kind
B2
Abstract

A raking receiver is provided in a wireless network. The raking receiver includes an antenna, first through Nth wavelet forming networks, first through Nth weighting mixers, a summer, a path mixer, and a signal processing circuit. The antenna receives an incoming signal. The first through Nth wavelet forming networks produce first through Nth locally generated wavelets. The first through Nth weighting mixers multiply the first through Nth locally generated wavelets by first through Nth weighting values, respectively, to produce first through Nth weighted wavelets. The summer adds together the first through Nth weighted wavelets to produce a weighted correlation input signal. The path mixer multiplies the incoming signal with the weighted correlation input signal to produce a correlated signal. And the signal processing circuit receives the correlated signal and produces a digital bit value. N is preferably an integer greater than 1.

Claims (95)

1. A raking receiver in a wireless network, comprising:

an antenna for receiving an incoming signal;

first through N th main path wavelet forming networks for producing first through N th locally generated main wavelets, respectively;

first through N th main path weighting mixers for multiplying the first through N th locally generated main wavelets by first through N th main weighting values, respectively, to produce first through N th main weighted wavelets;

a main path summer for adding together the first through N th main weighted wavelets to produce a weighted main correlation input signal;

a main path mixer for multiplying the incoming signal with the weighted main correlation input signal to produce a main correlated signal; and

a main path signal processing circuit for receiving the main correlated signal and producing a digital bit value,

wherein N is an integer greater than 1.

2. A raking receiver in a wireless network, as recited in claim 1 , wherein the main path signal processing circuit further comprises: a main path filtering circuit for filtering the main correlated signal to produce a main filtered signal.

3. A raking receiver in a wireless network, as recited in claim 2 , wherein the main path signal processing circuit further comprises: a main path analog-to-digital converter for converting the main filtered signal to a digital bit value.

4. A raking receiver in a wireless network, as recited in claim 2 , wherein the main path signal processing circuit further comprises: a main path amplifier chain for amplifying the main correlated signal before it is provided to the main path filtering circuit.

5. A raking receiver in a wireless network, as recited in claim 1 , wherein the main path signal processing circuit further comprises: a main path integrating circuit for integrating the main correlated signal to produce a main integrated signal.

6. A raking receiver in a wireless network, as recited in claim 5 , wherein the main path signal processing circuit further comprises: a main path analog-to-digital converter for converting the main integrated signal to a digital bit value.

7. A raking receiver in a wireless network, as recited in claim 5 , wherein the main path signal processing circuit further comprises: a main path amplifier chain for amplifying the main correlated signal before it is provided to the main path integrating circuit.

8. A raking receiver in a wireless network, as recited in claim 5 , wherein the main path integrating circuit further comprises:

a first integrator;

a second integrator;

a third integrator;

an input switch that can select one of the first, second, and third integrators to connect to the main path mixer; and

an output switch that can select one of the first, second, and third integrators to connect to a main path analog-to-digital converter,

wherein for every integration period, the input switch selects one of the first, second, and third integrators as an integrating integrator to integrate the main correlated signal, the output switch selects one of the first, second, and third integrators as a holding integrator to output the main integrated signal, and one of the first, second, and third integrators operates as a dumping integrator to dump any information it had previously stored, and

wherein for every integration period, the integrating, holding and dumping integrators are each different ones of the first, second, and third integrators.

9. A raking receiver in a wireless network, as recited in claim 1 , wherein phases of each of the first through N th locally generated main wavelets can be independently varied by the first through N th main path wavelet forming networks, respectively.

10. A raking receiver in a wireless network, as recited in claim 1 , further comprising:

first through M th error path wavelet forming networks for producing first through M th locally generated error wavelets, respectively;

first through M th error path weighting mixers for multiplying the first through M th locally generated error wavelets by first through M th error weighting values, respectively, to produce first through M th error weighted wavelets;

an error path summmer for adding together the first through M th error weighted wavelets to produce a weighted error correlation input signal;

an error path mixer for multiplying the incoming signal with the weighted error correlation input signal to produce an error correlated signal; and

an error path signal processing circuit for receiving the error correlated signal and producing a digital error-tracking signal,

wherein M is an integer greater than 1.

11. A raking receiver in a wireless network, as recited in claim 10 , wherein the error path signal processing circuit further comprises: an error path filtering circuit for filtering the error correlated signal to produce an error filtered signal.

12. A raking receiver in a wireless network, as recited in claim 11 , wherein the error path signal processing circuit further comprises: an error path analog-to-digital converter for converting the error filtered signal to a digital bit value.

13. A raking receiver in a wireless network, as recited in claim 11 , wherein the error path signal processing circuit further comprises: an error path amplifier chain for amplifying the error correlated signal before it is provided to the error path filtering circuit.

14. A raking receiver in a wireless network, as recited in claim 10 , wherein the error path signal processing circuit further comprises: an error path integrating circuit for integrating the error correlated signal to produce an error integrated signal.

15. A raking receiver in a wireless network, as recited in claim 14 , wherein the error path signal processing circuit further comprises: an error path analog-to-digital converter for converting the error integrated signal to the digital error-tracking signal.

16. A raking receiver in a wireless network, as recited in claim 14 , wherein the error path signal processing circuit further comprises: an error path amplifier chain for amplifying the error correlated signal before it is provided to the error path integrating circuit.

17. A raking receiver in a wireless network, as recited in claim 15 , wherein the error path integrating circuit further comprises:

a first integrator;

a second integrator;

a third integrator;

an input switch that can select one of the first, second, and third integrators to connect to the error path amplifier chain; and

an output switch that can select one of the first, second, and third integrators to connect to the error path analog-to-digital converter,

wherein for every integration period, the input switch selects one of the first, second, and third integrators as a sample integrator to sample the error amplified signal, the output switch selects one of the first, second, and third integrators as a hold integrator to output the error integrated signal, and one of the first, second, and third integrators operates as a dump integrator to dump any information it had previously stored, and

wherein for every integration period, the sample, hold and dump integrators are each different ones of the first, second, and third integrators.

18. A raking receiver in a wireless network, as recited in claim 10 , wherein phases of each of the first through M th error wavelets can be independently varied by the first through M th error path wavelet forming networks, respectively.

19. A raking receiver in a wireless network, as recited in claim 10 , wherein M is equal to N.

20. A raking receiver in a wireless network, comprising:

an antenna for receiving an incoming signal;

a wavelet forming circuit for producing first through N th weighted main wavelets and first through N th weighted error wavelets;

a main path summer for adding together the first through N th weighted main wavelets to produce a main correlation input signal;

an error path summer for adding together the first through N th weighted error wavelets to produce an error correlation input signal;

a main path mixer for multiplying the incoming signal with the main correlation input signal to produce a main correlated signal;

an error path mixer for multiplying the incoming signal with the error correlation input signal to produce an error correlated signal;

a main path signal processing circuit for receiving the main correlated signal and producing a digits bit value; and

an error path signal processing circuit for receiving the error correlated signal and producing a digital error-tracking signal,

wherein N is an integer greater than 1.

21. A raking receiver in a wireless network, as recited in claim 20 , wherein the main path signal processing circuit further comprises:

a main path amplifier chain for amplifying the main correlated signal to produce a main amplified signal;

a main path integrator circuit fOr integrating the main amplified signal to produce a main integrated signal; and

a main path analog-to-digital converter for converting the main integrated signal to the digital bit value.

22. A raking receiver in a wireless network, as recited in claim 21 , wherein the main path integrator circuit farther comprises:

a first integrator;

a second integrator;

a third integrator;

an input switch that can select one of the first, second, and third integrators to connect to the main path amplifier chain; and

an output switch that can select one of the first, second, and third integrators to connect to the main path analog-to-digital converter,

wherein for every integration period, the input switch selects one of the first, second, and third integrators as a sample integrator to sample the main amplified signal, the output switch selects one of the first, second, and third integrators as a hold integrator to output the main integrated signal, and one of the first, second, and third integrators operates as a dump integrator to dump any information it had previously stored, and

wherein for every integration period, the sample, hold and dump integrators are each different ones of the first, second, and third integrators.

23. A raking receiver in a wireless network, as recited in claim 20 , wherein the error path signal processing circuit further comprises:

an error path amplifier chain for amplifying the error correlated signal to produce an error amplified signal;

an error path integrator circuit for integrating the error amplified signal to produce an error integrated signal; and

an error path analog-to-digital converter for converting the error integrated signal to the digital error-tracking signal.

24. A raking receiver in a wireless network, as recited in claim 23 , wherein the error path integrator circuit further comprises:

a first integrator;

a second integrator;

a third integrator;

an input switch that can select one of the first, second, and third integrators to connect to the error path amplifier chain; and

an output switch that can select one of the first, second, and third integrators to connect to the error path analog-to-digital converter,

wherein for every integration period, the input switch selects one of the first, second, and third integrators as a sample integrator to sample the error amplified signal, the output switch selects one of the first, second, and third integrators as a hold integrator to output the error integrated signal, and one of the first, second, and third integrators operates as a dump integrator to dump any information it had previously stored, and

wherein for every integration period, the sample, hold and dump integrators are each different ones of the first, second, and third integrators.

25. A raking receiver in a wireless network, as recited in claim 20 , wherein phases of each of the first through N th weighted error wavelets can be independently varied by the wavelet forming circuit.

26. A method of raking in a wireless network, comprising:

receiving a wireless signal;

generating first through N th locally generated main wavelets;

multiplying the first through N th locally generated main wavelets by first through N th main weighting values, respectively, to produce first through N th main weighted wavelets, respectively,

adding together the first through N th main weighted wavelets to produce a main correlation input signal; and

correlating the main correlation input signal with the received signal to produce a bit value,

wherein N is an integer greater than 1.

27. A method of raking in a wireless network, as recited in claim 26 , further comprising:

generating first through M th locally generated error wavelets;

multiplying the first through M th locally generated error wavelets by first through M th error weighting values, respectively, to produce first through M th error weighted wavelets;

adding together the first through M th error weighted wavelets to produce a error correlation input signal; and

correlating the error correlation input signal with the received signal to produce an error-tracking signal,

wherein M is an integer greater than 1.

28. A method of raking in a wireless network, as recited in claim 27 , wherein M is equal to N.

Assignments (23)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 4, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NORTH STAR INNOVATIONS INC.
Reel/Frame 037694/0264 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0225 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0670 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SECURITY AGREEMENT Recorded May 13, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 024397/0001 →
SECURITY AGREEMENT Recorded Jul 11, 2008
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A.
Reel/Frame 021217/0368 →
SECURITY AGREEMENT Recorded Feb 2, 2007
From: FREESCALE SEMICONDUCTOR, INC.; FREESCALE ACQUISITION CORPORATION; FREESCALE ACQUISITION HOLDINGS CORP.; FREESCALE HOLDINGS (BERMUDA) III, LTD.
To: CITIBANK, N.A. AS COLLATERAL AGENT
Reel/Frame 018855/0129 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 15, 2005
From: MOTOROLA, INC.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 015735/0156 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 7, 2004
From: MOTOROLA, INC
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 015360/0718 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 23, 2003
From: XTREMESPECTRUM, INC.
To: MOTOROLA, INC.
Reel/Frame 014815/0242 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 8, 2003
From: MCCORKLE, JOHN W.
To: XTREMESPECTRUM, INC.
Reel/Frame 014598/0426 →