Semiconductor memory device and defect remedying method thereof
View Patent ↗A semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. This structure in which the peripheral circuits are arranged at the center portion of the chip permits the longest signal transition paths to be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.
1. A semiconductor device formed in a rectangle region on a semiconductor substrate, said rectangle region comprising a first region formed along an imaginary line which intersects a first middle point of a first side of said rectangle region and a second middle point of an opposite side of said first side, wherein said first region divides said rectangle region to form a second region and a third region, said semiconductor device comprising:
a first memory array having a plurality of dynamic memory cells formed in said second region;
a second memory array having a plurality of dynamic memory cells formed in said third region;
a plurality of bonding pads formed in said first region; and
a voltage drop circuit formed in said first region, wherein said voltage drop circuit has an input terminal receiving an external voltage through one of said bonding pads and an output terminal outputting an internal power voltage.
2. A semiconductor device according to claim 1 ,
wherein said semiconductor device is comprised in a Lead On Chip (LOC) package.
3. A semiconductor device according to claim 1 ,
wherein said voltage drop circuit generates said internal power voltage based on said external voltage.
4. A semiconductor device according to claim 2 ,
wherein said voltage drop circuit generates said internal power voltage based on said external voltage.
5. A semiconductor device formed in a rectangle region on a semiconductor substrate, said rectangle region comprising a first region formed along an imaginary line which intersects a first middle point of a first side of said rectangle region and a second middle point of an opposite side of said first side, wherein said first region divides said rectangle region to form a second region and a third region, said semiconductor device comprising:
a first memory array having a plurality of dynamic memory cells formed in said second region;
a second memory array having a plurality of dynamic memory cells formed in said third region;
a plurality of bonding pads formed in said first region; and
means for generating an internal power voltage formed in said first region, wherein said generating means comprises means for receiving an external voltage through one of said bonding pads, means for generating the internal power voltage from the external voltage and means for outputting said internal power voltage from an output terminal.
6. A semiconductor device according to claim 5 , wherein said means for generating the internal power voltage from the external voltage comprises a voltage drop circuit.