IP Library Granted Patent US 6,963,191
Granted Patent B1
US 6,963,191 · App. 10/683,845 · Granted Nov 8, 2005

Self-starting reference circuit

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Quick Facts
Patent No.
US 6,963,191
App. No.
10/683,845
Granted
Nov 8, 2005
Kind
B1
Abstract

A reference circuit provides a reference electrical characteristic such as a current or voltage using a low-threshold field effect transistor (FET) for improved start-up operation. The use of a low-threshold FET eliminates a stable operating point from occurring at zero current allowing the elimination of additional startup circuitry thereby providing power and space savings, particularly in analog CMOS circuitry. Additionally, the use of a low-threshold FET allows a lower voltage requirement from the power supply providing additional power savings.

Claims (20)

1. A self-starting reference circuit for providing a reference electrical characteristic comprising:

a current mirror including a first p-channel field effect transistor (FET) and a second p-channel FET configured to supply a reference current across the first FET and a mirrored output current across the second FET, each p-channel FET having a gate, a source and a drain wherein the gates of these FETs are connected, the sources are connected to a power supply, and the drain of the second FET is connected to the gates of these FETs; and

a current source including a first n-channel FET which is a low-threshold n-channel FET having a source, a gate and a drain, the gate of the low-threshold FET having a gate threshold voltage and being connected to the drain of the first p-channel FET and the drain of the low-threshold n-channel FET being connected to the drain of the second p-channel FET, the current source further including a reference regulator circuit for receiving the reference current from the drain of the first p-channel transistor and a reference output circuit for receiving the mirrored output current flowing from the source of the first low-threshold n-channel FET and outputting a reference electrical characteristic.

2. The self-starting reference circuit of claim 1 wherein the gate threshold voltage is about zero volts.

3. The self-starting reference circuit of claim 1 wherein the gate threshold voltage is slightly negative.

4. The self-starting reference circuit of claim 1 wherein the circuit is implemented in complementary metal-oxide semiconductor (CMOS).

5. The self-starting reference circuit of claim 1 wherein the circuit is implemented in analog CMOS.

6. The self-starting reference circuit of claim 1 wherein the low-threshold FET lacks a positive threshold voltage implant.

7. The self-starting reference circuit of claim 1 further comprises a second low-threshold n-channel FET having a gate, a source and a drain, its drain connected to the drain of the first p-channel transistor and to its own gate, its gate connected to the gate of the first low-threshold FET, and its source connected to the reference regulator circuit;

said reference regulator circuit comprises a bipolar junction transistor (BJT) having an emitter, a base and a collector, the emitter being coupled to the source of the second low-threshold n-channel FET and the collector and base being coupled to a ground; and

said reference output circuit comprising a resistance coupled between the source of the low-threshold transistor and ground.

8. The self-starting reference circuit of claim 6 wherein the circuit is implemented in Bi-CMOS.

9. The self-starting reference circuit of claim 1 wherein

said reference regulator circuit comprises a positive threshold voltage n-channel FET having a gate, source and drain, the drain connected to the drain of the first p-channel transistor, its gate connected to the source of the low-threshold FET, and its source being coupled to a ground; and

said reference output circuit comprising a resistance coupled between the source of the low-threshold transistor and ground.

10. In a self-starting reference circuit for providing a reference electrical characteristic comprising a current mirror including a first p-channel field effect transistor (FET) and a second p-channel FET configured to supply a reference current across the first FET and a mirrored output current across the second FET, each p-channel FET having a gate, a source and a drain wherein the gates of these FETs are connected, the sources are connected to a power supply, and the drain of the second FET is connected to the gates of these FETs, and a current source including a low-threshold n-channel FET having a source, a gate and a drain, the gate of the low-threshold FET being connected to the drain of the first p-channel FET and the drain of the low-threshold n-channel FET being connected to the drain of the second p-channel FET, the current source further including a reference regulator circuit for receiving the reference current from the drain of the first p-channel transistor and a reference output circuit for receiving the mirrored output current flowing from the source of the low-threshold n-channel FET and outputting a reference electrical characteristic, a method for operating a self-starting reference circuit comprising:

the low-threshold FET generating a current across its transistor;

generating a voltage across the reference output circuit based on the current;

generating a voltage across the reference regulator based on the voltage across the reference output circuit; and

providing a differential voltage between the power supply and the gates of the p-channel transistors causing forward active operation of the p-channel transistors.

Assignments (10)
INTELLECTUAL PROPERTY BUY-IN AGREEMENT/ASSIGNMENT Recorded Apr 4, 2023
From: MICREL LLC
To: MICROCHIP TECHNOLOGY INCORPORATED
Reel/Frame 063241/0771 →
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 10, 2003
From: MCCALMONT, JONATHAN S.
To: MICREL INC.
Reel/Frame 014602/0166 →