Method for forming a dielectric spacer in a non-volatile memory device
View Patent ↗Embodiments of the present invention relate to a method for fabricating a Vss line in a memory device, which comprises: forming a plurality of memory cells above a semiconductor substrate, forming a channel between two of the memory cells, forming an oxide/nitride/oxide stack above the memory cells and the channel, removing a portion of the oxide/nitride/oxide stack between the memory cells to expose the semiconductor substrate, removing the oxide/nitride/oxide stack above the gates of the memory cells, forming a plurality of source regions in the substrate between the memory cells, forming a poly-silicon layer above the memory cells and the channel to connect to the source regions, and removing a sufficient portion of the poly-silicon layer to form a Vss line.
1. A method for fabricating a Vss line in a memory device, comprising:
forming a plurality of memory cells above a semiconductor substrate;
forming a channel between two of said memory cells;
forming an oxide/nitride/oxide stack above said memory cells and said channel;
removing a portion of said oxide/nitride/oxide stack between said memory cells to expose said semiconductor substrate;
removing said oxide/nitride/oxide stack above the gates of said memory cells;
forming a plurality of source regions in said substrate between said memory cells;
forming a poly-silicon layer above said memory cells and said channel to connect to said source regions; and
removing a sufficient portion of said poly-silicon layer to form a Vss line.
2. The method as recited in claim 1 wherein said memory cells are implemented as flash memory cells.
3. The method as recited in claim 2 wherein said memory cells comprise:
a tunnel oxide above said semiconductor substrate;
a floating gate above said tunnel oxide;
an isolating region above said floating gate; and
a control gate above said isolating region, wherein said memory cell is programmed by storing a charge in said floating gate and current flow between said source and said drain is affected by said stored charge.
4. The method as recited in claim 3 wherein said isolating region comprises:
a first oxide layer above said floating gate;
a nitride layer above said first oxide layer; and
a second oxide layer above said nitride layer.
5. The method as recited in claim 4 wherein said oxide is an oxide of silicon.
6. The method as recited in claim 4 wherein said nitride is a nitride of silicon.
7. The method as recited in claim 1 wherein said channel is a Vss channel.
8. The method as recited in claim 1 wherein said forming an oxide/nitride/oxide stack comprises:
forming a first oxide layer above said semiconductor substrate;
forming a nitride layer above said first oxide layer; and
forming a second oxide layer above said nitride layer.
9. The method as recited in claim 8 wherein said oxide is an oxide of silicon.
10. The method as recited in claim 9 wherein said nitride is a nitride of silicon.