Method for forming robust solder interconnect structures by reducing effects of seed layer underetching
View Patent ↗A method for forming an interconnect structure for a semiconductor device includes defining a via in a passivation layer so as expose a top metal layer in the semiconductor device. A seed layer is formed over the passivation layer, sidewalls of the via, and the top metal layer. A barrier layer is formed over an exposed portion of the seed layer, the exposed portion defined by a first patterned opening. The semiconductor device is annealed so as to cause atoms from the barrier layer to diffuse into the seed layer thereunderneath, wherein the annealing causes diffused regions of the seed layer to have an altered electrical resistivity and electrode potential with respect to undiffused regions of the seed layer.
1. A method for forming an interconnect structure for a semiconductor device, the method comprising:
defining a via in passivation layer so as expose a top metal layer in the semiconductor device;
forming a seed layer over said passivation layer, sidewalls of said via, and said top metal layer;
forming a barrier layer over an exposed portion of said seed layer, said exposed portion defined by, a first patterned opening;
annealing the semiconductor device so as to cause atoms from said barrier layer to diffuse into said seed layer thereunderneath; and
following said annealing, forming a solder material over said barrier layer using a second patterned opening;
wherein said annealing causes diffused regions of said seed layer to have an altered electrical resistivity and electrode potential with respect to undiffused regions of said seed layer, and wherein said second patterned opening is configured so as to have a lager diameter than said first patterned opening.
2. The method of claim 1 , further comprising etching said seed layer, following said annealing, so as to define a ball limiting metallurgy (BLM), wherein remaining portions of said seed layer do not undercut said barrier layer.
3. The method of claim 1 , further comprising:
following said annealing, forming a solder material over said barrier layer using said first patterned opening.
4. The method of claim 3 , wherein said first patterned opening is formed using a photoresist material that is capable of withstanding temperatures generated during said annealing.
5. A method for forming an interconnect structure for a semiconductor device the method comprising:
defining a via in a passivation layer so as expose a top metal layer in the semiconductor device;
forming a seed layer over said passivation layer sidewalls of said via, and said top metal layer;
forming a barrier layer over an exposed portion of said seed layer, said exposed portion defined by a first patterned opening, and
annealing the semiconductor device so as to cause atoms from said barrier layer to diffuse into said seed layer thereunderneath;
wherein said annealing causes diffused regions of said seed layer to have an altered electrical resistivity and electrode potential with respect to undiffused regions of said seed layer, and wherein said annealing is implemented at a temperature and a duration so as to cause atoms from said barrier layer to diffuse into said seed layer by about one micron in x, y and z-directions.
6. The method of claim 5 , wherein said annealing results in an increased electrical resistivity of said diffused regions of said seed layer by about one order of magnitude.
7. The method of claim 5 , wherein:
said seed layer comprises a titanium-tungsten/chrome-copper/copper (TiW/CrCu/Cu) layer; and
said barrier layer comprises a nickel/copper layer.
8. The method of claim 7 , wherein copper and chrome copper portions of seed layer are removed by electroetching.
9. The method of claim 7 , wherein said annealing is implemented at temperature of about 350 to about 380° C. for a duration of about 30 to about 45 minutes.
10. A method for introducing a self etch stop mechanism within a metallic thin film, the method comprising:
forming overlayer upon the thin film;
annealing the thin film so as to cause atoms from said overlayer to diffuse into the thin film thereunderneath;
wherein said annealing causes diffused regions of the thin film to have an altered electrical resistivity and electrode potential with respect to undiffused regions of the thin film and wherein said annealing is implemented at a temperature and a duration so as to cause atoms from said overlayer to diffuse into the thin film by about one micron in x, y and z-directions.
11. The method of claim 10 , wherein said annealing results in an altered electrical resistivity and electrode potential of said diffused regions of the thin film by about one order of magnitude.
12. The method of claim 10 , wherein:
the thin film includes a copper layer; and
said over-layer includes a nickel/copper layer.