IP Library Granted Patent US 7,575,941
Granted Patent B2
US 7,575,941 · App. 10/710,732 · Granted Aug 18, 2009

Method of manufacturing photodiode

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Quick Facts
Patent No.
US 7,575,941
App. No.
10/710,732
Granted
Aug 18, 2009
Kind
B2
Abstract

A method of manufacturing of a photodiode is provided. The photodiode is formed on a substrate of a first conductive type. First, an isolation structure is formed in the substrate to define a photosensitive area in the substrate. Thereafter, trenches are formed in the substrate. Next, a doped layer of a second conductive type is formed on the substrate. The doped layer covers at least the inner wall of the trenches and a top portion of the substrate. The method of fabricating the photodiode can reduce overall processing time and cost and improve production efficiency.

Claims (15)

1. A method of fabricating a photodiode, comprising the steps of:

providing a substrate;

forming a well region of a first conductive type in the substrate;

forming an isolation structure in the well region of the substrate to define a photosensitive area on the substrate;

forming a plurality of trenches in the well region of substrate within the photosensitive area;

forming a buffer layer of a semiconductor material over the well region of the substrate, wherein the buffer layer covers the interior walls of the trenches and the surface of the well region of the substrate within the photosensitive area;

forming a doped layer of a second conductive type directly over the buffer layer; and

performing an annealing operation to drive dopants within the doped layer into the buffer layer and form a junction of the second conductive type and the first conductive type within the buffer layer.

2. The method of claim 1 , wherein the step of forming the doped layer comprises performing a chemical vapor deposition process.

3. The method of claim 1 , wherein a material constituting the doped layer is selected from the group consisting of doped polysilicon and doped epitaxial silicon.

4. The method of claim 1 , wherein the step of forming the buffer layer further comprises performing a chemical vapor deposition process.

5. The method of claim 1 , wherein a material constituting the buffer layer is selected from the group consisting of polysilicon and epitaxial silicon.

6. The method of claim 1 , wherein the first conductive type is P-type and the second conductive type is N-type.

7. The method of claim 1 , wherein the first conductive type is N-type and the second conductive type is P-type.

8. The method of claim 1 , wherein the doped layer completely fills the trenches.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2019
From: POWERCHIP TECHNOLOGY CORPORATION
To: POWERCHIP SEMICONDUCTOR MANUFACTURING CORPORATION
Reel/Frame 049746/0981 →
CHANGE OF NAME Recorded Jun 28, 2019
From: POWERCHIP SEMICONDUCTOR CORP.
To: POWERCHIP TECHNOLOGY CORPORATION
Reel/Frame 049629/0240 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 30, 2004
From: CHANG, KO-HSING; CHANG, SU-YUAN
To: POWERCHIP SEMICONDUCTOR CORP.
Reel/Frame 014917/0382 →