IP Library Assignment 049629/0240
Patent Assignment
Reel/Frame 049629/0240

Change of Name

Recorded: 2019-06-28 Pages: 3
Assignor
POWERCHIP SEMICONDUCTOR CORP.
Executed: 2010-08-09
Assignee
POWERCHIP TECHNOLOGY CORPORATION
NO. 12, LI-HSIN ROAD 1, HSINCHU SCIENCE PARK,, HSINCHU, TAIWAN
Covered Properties (20)
Method of Manufacturing a Dual Bit Flash Memory
Patent: 7,205,189 →
Application: 10/710,672 →
Publication: US 2005/0227434
Method of Manufacturing Photodiode
Patent: 7,575,941 →
Application: 10/710,732 →
Publication: US 2005/0227402
[Split-Gate Flash Memory Structure and Method of Manufacture]
Patent: 6,867,099 →
Application: 10/710,784 →
Publication: US 2004/0259310
Support Stand
Patent: 6,914,732 →
Application: 10/710,853 →
Method of Managing Wafer Defects
Patent: 7,412,090 →
Application: 10/711,310 →
Publication: US 2006/0050950
Method of Manufacturing Non-Volatile Memory Cell
Patent: 7,060,560 →
Application: 10/711,511 →
Publication: US 2005/0233523
Flash Memory Cell and Fabricating Method Thereof
Patent: 7,192,832 →
Application: 10/711,535 →
Publication: US 2005/0042826
Silicon-On-Insulator Device Structure
Patent: 7,019,582 →
Application: 10/711,624 →
Publication: US 2005/0029590
Operational Model for Simulating Manufacture Flow and Simulating Method Thereof
Patent: 7,221,994 →
Application: 10/904,383 →
Publication: US 2005/0278161
Non-Volatile Memory, Non-Volatile Memory Array and Manufacturing Method Thereof
Patent: 7,180,128 →
Application: 10/904,478 →
Publication: US 2005/0253182
Method of Fabricating a Flash Memory Cell
Patent: 7,029,973 →
Application: 10/904,514 →
Publication: US 2005/0090057
Flash Memory Cell and Fabricating Method Thereof
Patent: 7,235,839 →
Application: 10/904,749 →
Publication: US 2006/0024887
Method of Defect Inspection
Patent: 7,382,451 →
Application: 10/904,873 →
Publication: US 2005/0248756
Flash Memory Cell
Patent: 7,109,082 →
Application: 10/905,189 →
Publication: US 2006/0008981
Method of Manufacturing Semiconductor Device
Patent: 7,056,787 →
Application: 10/905,610 →
Publication: US 2005/0233519
Split Gate Flash Memory Cell and Manufacturing Method Thereof
Patent: 7,358,134 →
Application: 10/907,781 →
Publication: US 2006/0234444
Method for Forming a Titanium Nitride Layer
Patent: 7,030,015 →
Application: 10/941,939 →
Publication: US 2005/0053722
Method of Fabricating a Photosensitive Structure
Patent: 7,125,738 →
Application: 10/963,659 →
Publication: US 2006/0084194
Capacity Management System and Method
Patent: 7,035,704 →
Application: 10/988,527 →
Publication: US 2006/0004473
Method of Forming Si Tip by Single Etching Process and Its Application for Forming Floating Gate
Patent: 7,259,051 →
Application: 11/050,963 →
Publication: US 2006/0178011
Related Assignments (4)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest Jul 14, 2019
From: POWERCHIP TECHNOLOGY CORPORATION
To: POWERCHIP SEMICONDUCTOR MANUFACTURING CORPORATION
Reel/Frame 049746/0981 →
Assignment of Assignor's Interest Jul 14, 2019
From: POWERCHIP TECHNOLOGY CORPORATION
To: POWERCHIP SEMICONDUCTOR MANUFACTURING CORPORATION
Reel/Frame 049747/0017 →
Assignment of Assignor's Interest Apr 8, 2020
From: POWERCHIP SEMICONDUCTOR MANUFACTURING CORPORATION
To: POWERCHIP TECHNOLOGY CORPORATION
Reel/Frame 052337/0735 →
Assignment of Assignor's Interest Sep 7, 2020
From: POWERCHIP TECHNOLOGY CORPORATION
To: NEXCHIP SEMICONDUCTOR CORPORATION
Reel/Frame 053704/0522 →