IP Library Granted Patent US 7,382,451
Granted Patent B2
US 7,382,451 · App. 10/904,873 · Granted Jun 3, 2008

Method of defect inspection

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Quick Facts
Patent No.
US 7,382,451
App. No.
10/904,873
Granted
Jun 3, 2008
Kind
B2
Abstract

A plurality of cassettes, each having a plurality of wafers respectively having a first defect information, is selected. Each of the cassettes is then assigned to a corresponding tool having at least one reaction chamber, and the wafers are substantially equally assigned to the reaction chambers. A first process is then performed on each of the wafers in the reaction chamber. Finally, a first defect inspection process is performed on each of the wafers.

Claims (16)

1. A method of defect inspection for inspecting production errors of a plurality of tools, each tool comprising at least one reaction chamber, the method comprising:

performing a dispatching process comprising:

selecting a plurality of cassettes, each cassette comprising a plurality of wafers, each wafer comprising a first defect inspection information;

assigning each of the cassettes to a corresponding tool for ensuring each of the tools comprises at least one cassette; and

assigning the wafers in the cassettes to each of the reaction chambers in each of the tools, respectively, for ensuring each of the reaction chambers comprises at least one wafer;

performing a first process on each of the wafers in the reaction chamber;

performing a first defect inspection process on each of the wafers, performing a first procedure prior to the first process, wherein the first procedure comprises:

performing a second process on each of the wafers; and

performing a predetermined defect inspection process on the wafers to obtain the first defect inspection information, each of the first defect inspection information comprising the location and numbers of defects on the corresponding wafer;

performing the first defect inspection process on the wafers to obtain a second defect inspection information corresponding to each of the wafers, the second defect inspection information comprising at least the location and numbers of defects on the corresponding wafer, wherein upon when the number of defects in the second defect inspection information is significantly less than that in the first defect inspection information, the defects formed prior to the performance of the second process is thereby indicated to be non-killer defects, and a review towards the second process is thereby neglected; and upon when the number of defects in the second defect inspection information is significantly greater than that as in the first defect inspection information, and most of the locations of the defects shown in the second defect inspection information are different from those shown in the first defect inspection information, abnormality of the second process is thereby indicated.

2. The method of claim 1 wherein the method of defect inspection further comprises:

determining whether the second defect inspection information is within an allowable specification.

3. The method of claim 2 wherein the wafers with the second defect inspection information within the allowable specification is capable of being used for subsequent manufacturing processes.

4. The method of claim 2 wherein a comparing step is performed on the wafers with the second defect inspection information out of the allowable specification to compare the first defect information with the second defect inspection information of the corresponding wafer.

5. The method of claim 1 wherein each of the cassettes is a sampling cassette, each of the wafers is a sampling wafer, and each of the sampling wafers comprises a product wafer.

6. The method of claim 1 wherein either the first process or the second process comprises either a thin film deposition process, an ion implantation process, an etching process or a lithography process.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2019
From: POWERCHIP TECHNOLOGY CORPORATION
To: POWERCHIP SEMICONDUCTOR MANUFACTURING CORPORATION
Reel/Frame 049747/0017 →
CHANGE OF NAME Recorded Jun 28, 2019
From: POWERCHIP SEMICONDUCTOR CORP.
To: POWERCHIP TECHNOLOGY CORPORATION
Reel/Frame 049629/0240 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 1, 2004
From: LIN, LONG-HUI; CHEN, CHIA-YUN
To: POWERCHIP SEMICONDUCTOR CORP.
Reel/Frame 015407/0176 →