Method of fabricating a flash memory cell
View Patent ↗A method of forming a flash memory cell. A tunnel oxide layer, a floating gate layer, and a dielectric layer are formed on a substrate. A control gate layer is formed on the dielectric layer and then etched to form two control gates. The control gates are oxidized to form a plurality of second oxide layers on surfaces of the control gates and aside the control gates. The dielectric layer and the floating gate layer are etched by utilizing the second oxide layers as a mask to form a floating gate underneath each of the control gates. A source is formed between the floating gates. The floating gates and the substrate are oxidized to form a plurality of first oxide layers aside the floating gates and form a third oxide layer on a surface of the source.
1. A method of forming a flash memory cell, the method comprising:
forming a tunnel oxide layer, a floating gate layer, and a dielectric layer on a substrate in sequence;
forming a control gate layer on the dielectric layer;
etching the control gate layer to form two control gates;
oxidizing the control gates to form a plurality of first oxide layers on surfaces of the control gates and aside the control gates;
etching the dielectric layer and the floating gate layer by utilizing the first oxide layers as a mask to form floating gates underneath the control gates;
implanting ions into the substrate to form a source between the floating gates;
oxidizing the floating gates and the substrate to form a plurality of second oxide layers aside the floating gates and to form a third oxide layer on a surface of the source; and
forming an erasing gate on the third oxide layer, the erasing gate drawing electrons from either of the floating gates of the flash memory cell in an erasing operation.
2. The method of claim 1 , wherein the method of forming the erasing gate comprises:
depositing an erasing gate layer on the substrate; and
performing an etching back process to remove portions of the erasing gate layer and leave the residual of the erasing gate layer on the third oxide layer.
3. The method of claim 2 , wherein the method further includes a step of implanting ions into the substrate after the etching back process so as to form two drains, and the source is located between the drains.
4. The method of claim 1 , wherein the substrate is a silicon substrate.
5. The method of claim 1 , wherein a lateral width of each first oxide layer being larger than a lateral width of each second oxide layer.
6. The method of claim 1 , wherein a lateral width of each first oxide layer is approximately 500 Å to 800 Å.
7. The method of claim 1 , wherein a lateral width of each second oxide layer is approximately 200 Å.
8. The method of claim 1 , wherein a lateral width of each control gate is smaller than a lateral width of each floating gate.
9. The method of claim 1 , wherein a shape of a lateral cross section of the floating gates is thin on top and bottom and thick in the middle, and a shape of a lateral cross section of the second oxide layers is thick on top and bottom and thin in the middle.