IP Library Granted Patent US 7,125,738
Granted Patent B2
US 7,125,738 · App. 10/963,659 · Granted Oct 24, 2006

Method of fabricating a photosensitive structure

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,125,738
App. No.
10/963,659
Granted
Oct 24, 2006
Kind
B2
Abstract

A method of fabrication of a photosensitive device is disclosed. A substrate with at least an insulator layer formed thereon is provided. The insulator layer comprises a plurality of photoreceiving regions, and a plurality of conductive patterns are formed thereon without covering the photoreceiving regions. A dielectric layer is formed on the insulator and the conductive patterns, and polished by CMP thereof. The dielectric layer comprises a first dielectric layer formed by PECVD and a second dielectric layer formed by HDPCVD.

Claims (9)

1. A method for fabricating a photosensitive device, comprising the steps of:

providing a substrate with at least an insulator layer formed thereon, wherein the insulator layer comprises a plurality of photoreceiving regions therein, a plurality of conductive patterns are formed on the insulator layer without covering the photoreceiving regions;

forming a dielectric layer on the insulator and the conductive patterns; and

polishing the dielectric layer, wherein the dielectric layer comprises a first dielectric layer formed by PECVD and a second dielectric layer formed by HDPCVD.

2. The method as claimed in claim 1 , wherein the dielectric layer is silicon oxide or silicon oxynitride.

3. The method as claimed in claim 1 , wherein polishing of the dielectric layer is accomplished by CMP.

4. The method as claimed in claim 1 , wherein the conductive patterns have a thickness of 8000 Ř10000 Å.

5. The method as claimed in claim 1 , wherein the polished dielectric layer has a thickness of 2000 Ř4000 ŠA on the conductive patterns.

6. The method as claimed in claim 1 , further comprising forming a color filter layer on the dielectric layer, coating an upper dielectric layer on the color filter layer, forming a plurality of microlenses on the upper dielectric layer, and forming a protective layer on the microlenses.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2019
From: POWERCHIP TECHNOLOGY CORPORATION
To: POWERCHIP SEMICONDUCTOR MANUFACTURING CORPORATION
Reel/Frame 049746/0981 →
CHANGE OF NAME Recorded Jun 28, 2019
From: POWERCHIP SEMICONDUCTOR CORP.
To: POWERCHIP TECHNOLOGY CORPORATION
Reel/Frame 049629/0240 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 14, 2004
From: HUANG, MING-JENG; HSUE, CHEN-CHIU
To: POWERCHIP SEMICONDUCTOR CORP.
Reel/Frame 015893/0239 →