Low power content addressable memory
View Patent ↗A low power content addressable memory (CAM) device. The CAM device receives an N-bit comparand value and, in response, activates less than N compare lines within the CAM device to compare each of the N bits of the comparand value with contents of CAM cells coupled to the N compare lines.
1. A content addressable memory (CAM) device comprising:
an array of CAM cells;
a write mapping circuit to convert an input data word into a converted data word based on both data bits and mask bits within the input data word, the converted data word having one of at least two different patterns of constituent bits according to the state of a first control signal; and
a read/write circuit coupled to receive the converted data word from the write mapping circuit and coupled to the array of CAM cells to output the converted data word thereto.
2. The CAM device of claim 1 wherein the two different patterns of bits comprise equal numbers of bits.
3. The CAM device of claim 1 wherein the input data word includes data bits and mask bits with each of the data bits and mask bits constituting a respective data/mask bit pair, and wherein each set of four bits within the converted data word includes 2 R bits in a first state and the remaining bits in a second state if the first control signal selects a first conversion mode, R being the number of mask bits in a masking state within a group of two data/mask bit pairs.
4. The CAM device of claim 3 wherein each set of four bits within the converted data word includes R-2 bits in a first state and the remaining bits in a second state if the first control signal selects a second conversion mode.
5. The CAM device of claim 4 wherein the converted data word is complemented prior to being stored within the array of CAM cells if the first control signal selects the second conversion mode.
6. The CAM device of claim 3 wherein the converted data word is complemented prior to being stored within the array of CAM cells if the first control signal selects the first conversion mode.
7. The CAM device of claim 1 further comprising a write data selector having a first input port coupled to receive the converted data word from the write mapping circuit and a second input port coupled to receive the input data word, the write data selector being responsive to a second control signal to output either the converted data word or the input data word to the read/write circuit.
8. The CAM device of claim 1 further comprising a read mapping circuit coupled to receive a read data word from the read/write circuit and configured to convert the read data word into a converted data word having one of at least two different patterns of constituent bits according to the state of the first control signal.
9. A method of operation within a content addressable memory (CAM) device, the method comprising:
receiving a control signal;
receiving an input data word;
converting the input data word, based on both data bits and mask bits therein, into a converted data word having a first pattern of constituent bits if the control signal is in a first state;
converting the input data word, based on both the data bits and mask bits, into a converted data word having a second pattern of constituent bits if the control signal is in a second state; and
storing the converted data word in an array of CAM cells.
10. The method of claim 9 wherein the first pattern of constituent bits includes the same number of bits as the second pattern of constituent bits.
11. The method of claim 9 wherein the input data word includes data bits and mask bits with each of the data bits and mask bits constituting a respective mask/data bit pair, and wherein each set of four bits within the converted data word includes 2 R bits in a first state and the remaining bits in a second state if the control signal is in the first state, R being the number of mask bits in a masking state within a group of two data/mask bit pairs.
12. The method of claim 11 wherein each set of four bits within the converted data word includes R-2 bits in a first state and the remaining bits in a second state if the control signal is in the second state.
13. The method of claim 12 wherein the converted data word is complemented prior to being stored within the array of CAM cells if the control signal is in the second state.
14. The method of claim 11 wherein the converted data word is complemented prior to being stored within the array of CAM cells if the control signal is in the first state.